$ (make), make command

Make defines a number of default variables, such as common commands or command options, what CC, Cflags, and so on.
${make} is the name (or path) of the preset make command.
Make-p can view the current values of all predefined variables.

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In some large projects, we will put our different modules or different functions of the source files in different directories, we can write a directory in each directory of the makefile, which helps to make our makefile become more concise, Rather than writing everything in one makefile, it's hard to maintain our makefile, a technique that has great benefits for our module compilation and staging.

For example, we have a subdirectory called SubDir, which has a makefile file that indicates the compilation rules for the files in this directory. So the makefile that we have always controlled can write like this:

Subsystem

CD SubDir && $ (make)

It is equivalent to:

Subsystem

$ (make)-C subdir

The definition of the $ (make) macro variable means that perhaps our make requires some parameters, so defining a variable is more conducive to maintenance. These two examples are all meant to go into the "subdir" directory and then execute the make command.

We call this makefile "Master Makefile", and the makefile variable can be passed to the subordinate makefile (if you display the declaration), but will not overwrite the variable defined in the underlying makefile unless the "-E" parameter is specified.

$ (make), make command