2 k page k9k8g08 writepage readpage

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Static u32 writepage (u32 ADDR, u8 * BUF)
{
U32 I, MECC, secc;
U8 stat, TMP [6], value;

ADDR & = ~ 0x3f;

Initecc (); // reset ECC
Meccunlock (); // unlock the main ECC
Nfchipen (); // enable nandflash chip selection
Waitnfbusy (); // wait for a busy signal
Wrnfcmd (0x80); // page write command cycle 1

Wrnfaddr (0x00); // The column address a0 ~ A7
Wrnfaddr (0x00); // column address A8 ~ A11
Wrnfaddr (ADDR> 0) & 0xff); // The row address A12 ~ A19
Wrnfaddr (ADDR> 8) & 0xff); // The row address A20 ~ A27
Wrnfaddr (ADDR> 16) & 0xff); // The row address A28 ~ A30

For (I = 0; I <2048; I ++)
Wrnfdat (BUF [I]); // write a page of data

Waitnfbusy (); // wait for a busy signal
Mecclock (); // lock the ECC verification code of the main area
MECC = rdnfmecc (); // read the ECC verification code in the main zone.

// Convert the ECC verification code of the main area from the font to the byte type and save it to the zero-time array.
TMP [0] = (u8) (MECC & 0xff );
TMP [1] = (u8) (MECC> 8) & 0xff );
TMP [2] = (u8) (MECC> 16) & 0xff );
TMP [3] = (u8) (MECC> 24) & 0xff );

Seccunlock (); // unlock the ECC in the spare Zone

// Write the ECC value of the main area to the first four bytes of the spare area, that is, 2048th ~ 2051 address
Wrnfdat (TMP [0]);
Wrnfdat (TMP [1]);
Wrnfdat (TMP [2]);
Wrnfdat (TMP [3]);

Secclock (); // lock the ECC verification code in the spare Zone
SECC = rdnfsecc (); // read the ECC verification code in the spare area.

// Convert the ECC verification code in the spare area from a font to a byte type and save it to the zero-hour array.
TMP [4] = (u8) (SECC & 0xff );
TMP [5] = (u8) (SECC> 8) & 0xff );

// Write the ECC value of spare to 2052nd ~ of spare ~ 2053 address
Wrnfdat (TMP [4]);
Wrnfdat (TMP [5]);

Wrnfcmd (0x10); // page write command cycle 2
Waitnfbusy (); // wait for a busy signal
Wrnfcmd (0x70); // write read STATUS Command
Waitnfbusy (); // wait for a busy signal
Stat = rdnfdat (); // read status word
Nfchipds (); // disable nandflash chip selection
If (STAT & 0x01)
{
Markbadblk (ADDR); // mark Bad blocks
Puts ("writepage error! \ N "); // write operation failed
Return 0; // write operation failed
}
Puts ("writepage no error! \ N "); // write operation successful
Return 1; // write operation successful
}

 

Static void readpage (u32 ADDR, u8 * BUF)
{
U32 I, MECC, secc;
 
ADDR & = ~ 0x3f;

Initecc (); // reset ECC
Meccunlock (); // unlock the main ECC
Nfchipen (); // enable nandflash chip selection
Waitnfbusy (); // wait for a busy signal
Wrnfcmd (0x00); // page READ command cycle 1

Wrnfaddr (0x00); // The column address a0 ~ A7
Wrnfaddr (0x00); // column address A8 ~ A11
Wrnfaddr (ADDR> 0) & 0xff); // The row address A12 ~ A19
Wrnfaddr (ADDR> 8) & 0xff); // The row address A20 ~ A27
Wrnfaddr (ADDR> 16) & 0xff); // The row address A28 ~ A30
 
Wrnfcmd (0x30); // page READ command cycle 2
Waitnfbusy (); // wait for a busy signal
 
For (I = 0; I <2048; I ++)
Buf [I] = rdnfdat (); // reads a page of data
Waitnfbusy (); // wait for a busy signal

Mecclock (); // lock the ECC value of the main area

Seccunlock (); // unlock the ECC value in the spare Zone
 
MECC = rdnfdat32 (); // read the first four addresses in the spare area, that is, 2048 ~ 2051, the four bytes are the ECC values of the main zone
Buf [I + 1] = (u8) (MECC & 0xff); // put the ECC verification code of the read main area into the zero-hour array.
Buf [I + 2] = (u8) (MECC> 8) & 0xff); // put the ECC verification code of the read main area into the zero-hour array.
Buf [I + 3] = (u8) (MECC> 16) & 0xff); // put the ECC verification code of the read main area into the zero-hour array.
Buf [I + 4] = (u8) (MECC> 24) & 0xff); // put the ECC verification code of the read main area into the zero-hour array.

// Put the ECC verification code of the read main area into the corresponding position of nfmeccd0/1
Rnfmeccd0 = (MECC & 0xff00) <8) | (MECC & 0xff );
Rnfmeccd1 = (MECC & 0xff000000)> 8) | (MECC & 0xff0000)> 16 );

Secclock (); // lock the ECC value in the spare Zone

SECC = rdnfdat32 (); // read the four addresses in the spare area, that is, 2052 ~ 2055. The first two bytes are the ECC values in the spare zone.

Buf [I + 5] = (u8) (SECC & 0xff); // put the ECC verification code of the read spare area into the zero-hour array.
Buf [I + 6] = (u8) (SECC> 8) & 0xff); // put the ECC verification code of the read spare area into the zero-hour array.
Buf [I + 7] = (u8) (SECC> 16) & 0xff); // put the ECC verification code of the read spare area into the zero-hour array.
Buf [I + 8] = (u8) (SECC> 24) & 0xff); // put the ECC verification code of the read spare area into the zero-hour array.
Rnfseccd = (SECC & 0xff00) <8) | (SECC & 0xff); // place the ECC verification code in the read spare area to the corresponding position of nfseccd

Nfchipds (); // disable nandflash chip selection

If (rnfestat0) & 0x0f) = 0) // checks whether the main data area and spear date area have bit errors
Puts ("ECC no error! \ N "); // ECC Error
Else
Puts ("ECC error! \ N "); // No ECC Error
Puts ("0x % 8x \ n", (rnfestat0); // display the read rnfestat0 register