31.6410 Knowledge of memory

31.6410 Knowledge of memory

6410 of the address space distribution:

The S3C6410 processor has a 32-bit address bus with an addressing space of. The height is reserved peripheral area, the low 2GB area can be divided into two parts: main storage area and peripheral area.

The peripheral is primarily the address where the register resides.

The primary storage area is divided into: boot mirror, internal storage, static storage, reserved, dynamic storage:

Boot Mirror area: The role of this area, as its name says, is used to start the arm system. But this area does not have a fixed storage medium corresponding to it. Instead, the different boot media are mapped to the zone by modifying the startup options. For example, after selecting the Irom startup mode, the Irom is mapped to the region.

Internal storage: This area corresponds to the internal memory address, both Irom and SRAM are distributed across this interval. 0X08000000~0X0BFFFFFF corresponds to the internal ROM, but irom actually only 32KB, choose from Irom Start, the first run is the program BL0, this part of the code by Samsung curing. 0X0C000000~0X0FFFFFFF corresponds to the internal SRAM, the actual is 8KB steppingstone.

Static storage: This area is used to access devices that are hung on an external bus, such as nor Flash, Onenand, and so on. This area is divided into 6 banks, each bank is 128MB, the data width of the largest support 16bit, each bank by the chip select Xm0cs[0]~xm0cs[5] selected.

Dynamic storage: The region from the 0x50000000~0x6fffffff, divided into 2 intervals, respectively, accounting for 256MB, you can choose Xm1cs[0]~xm1cs[1] to carry out the selection of 2 intervals. The memory on our Development Board is arranged in this 6410 256MB DDR region, which is why 6410 of the memory address is starting from 0x50000000.

6410 of storage controllers:

The fifth chapter of S3c6410x.pdf is the DRAM CONTROLLER:

1.Program memc_cmd to ' 3 ' b100 which makes DRAM Controller, enter ' config ' state.

2.Write Memory Timing parameter, chip configuration, and ID configuration registers.

3.Wait 200us to allow SDRAM power and clock to stabilize. However, when the CPU starts working, power and clock would already be stabilized.

4.Execute memory initialization sequence.

5.Program memc_cmd to ' 3 ' b000 which makes DRAM Controller enter "Ready" state.

6.Check Memory Status field in Memc_stat until memory status becomes ' 2 ' bo1, which means ' ready '.

From the above description, it is known that 6410 of the storage controller initialization is to have the process: (2440 not required) so look at how the Uboot to initialize the storage controller. Verify that the uboot follows the steps above:

Open the Cpu_init in uboot/cpu/s3c64xx/s3c6410. S: This assembly file is for the board memory and storage controller initialization.

At the beginning of this Assembly a few lines of the file do not know what to do temporarily regardless of:

,

As seen from the note, this is the size of the bus that is set.

Chip Documentation:

In this register the main is to see:

Note: data[26:16] to data[31:16]

From above, if the [7] bit of the register is set to 0, then data[31:16] These 16 bits are the memory chip data pins. If it is 1, then these bits will be used by SROMC, which is set to 0.

0xd=0b00001101, so [7]=0, so is the data pin.

Followed by:

You can see that there is a corresponding data 0x04=0b100, the data write register is memc_cmd, which is consistent with the manual: 1. Program Memc_cmd to ' 3 ' b100 which makes DRAM Controller enter ' config ' state.

Follow the steps above:

Register Memc_cmd:

2.Write Memory Timing parameter, chip configuration, and ID configuration registers. This is the time parameter to write memory, chip configuration, configuration register, such as a series of register configuration operation: no look:

LDR R1, =DMC_DDR_REFRESH_PRD

STR R1, [R0, #INDEX_DMC_REFRESH_PRD]

LDR R1, =dmc_ddr_cas_latency

STR R1, [R0, #INDEX_DMC_CAS_LATENCY]

LDR R1, =dmc_ddr_t_dqss

STR R1, [R0, #INDEX_DMC_T_DQSS]

LDR R1, =DMC_DDR_T_MRD

STR R1, [R0, #INDEX_DMC_T_MRD]

LDR R1, =dmc_ddr_t_ras

STR R1, [R0, #INDEX_DMC_T_RAS]

LDR R1, =DMC_DDR_T_RC

STR R1, [R0, #INDEX_DMC_T_RC]

LDR R1, =DMC_DDR_T_RCD

LDR R2, =DMC_DDR_SCHEDULE_RCD

Orr R1, R1, R2

STR R1, [R0, #INDEX_DMC_T_RCD]

LDR R1, =DMC_DDR_T_RFC

LDR R2, =DMC_DDR_SCHEDULE_RFC

Orr R1, R1, R2

STR R1, [R0, #INDEX_DMC_T_RFC]

LDR R1, =DMC_DDR_T_RP

LDR R2, =DMC_DDR_SCHEDULE_RP

Orr R1, R1, R2

STR R1, [R0, #INDEX_DMC_T_RP]

LDR R1, =DMC_DDR_T_RRD

STR R1, [R0, #INDEX_DMC_T_RRD]

LDR R1, =DMC_DDR_T_WR

STR R1, [R0, #INDEX_DMC_T_WR]

LDR R1, =DMC_DDR_T_WTR

STR R1, [R0, #INDEX_DMC_T_WTR]

LDR R1, =dmc_ddr_t_xp

STR R1, [R0, #INDEX_DMC_T_XP]

LDR R1, =DMC_DDR_T_XSR

STR R1, [R0, #INDEX_DMC_T_XSR]

LDR R1, =DMC_DDR_T_ESR

STR R1, [R0, #INDEX_DMC_T_ESR]

LDR R1, =dmc1_mem_cfg

STR R1, [R0, #INDEX_DMC_MEMORY_CFG]

LDR R1, =dmc1_mem_cfg2

STR R1, [R0, #INDEX_DMC_MEMORY_CFG2]

LDR R1, =dmc1_chip0_cfg

STR R1, [R0, #INDEX_DMC_CHIP_0_CFG]

LDR R1, =dmc_ddr_32_cfg

STR R1, [R0, #INDEX_DMC_USER_CONFIG]

3.Wait 200us to allow SDRAM power and clock to stabilize. However, when the CPU starts working, power and clock would already be stabilized.

In the third step here, you can not do it. Skip over.

4.Execute Memory initialization sequence.

is the memory initialization sequence of execution:

1.Program Mem_cmd in Direct_cmd to ' 2 ' B11 which makes DRAM Controller issue ' NOP ' memory command.

2.Program mem_cmd in Direct_cmd to ' 2 ' b00 which makes DRAM Controller issue ' Prechargeall ' Memorycommand.

3.Program Mem_cmd in Direct_cmd to ' 2 ' b01 which makes DRAM Controller issue ' AutoRefresh ' Memorycommand.

4.Program mem_cmd in Direct_cmd to ' 2 ' B11 which makes DRAM Controller issue ' AutoRefresh ' Memorycommand.

5.Program mem_cmd to ' 2 ' B10 in Direct_cmd, which makes DRAM Controller issue ' MRS ' memory Command-bank address for EMRs m UST be set.

6.Program mem_cmd to ' 2 ' B10 in Direct_cmd, which makes DRAM Controller issue ' MRS ' memory command.-Bank address for MRS m UST be set.

1. In this memory initialization series, the first one is written to the mem_cmd bitof the Direct_cmd register B11, allowing the DRAM control register to issue a NOP command. (The above mem_cmd is 01 is wrong, the following is the right).

So what is written in the Directcmd register is: 0b11000000000000000000=0x000c0000. Look at the code in Uboot:

You can see that the Uboot is written in accordance with the chip manual, writing is also 0x0c0000.

2.Program mem_cmd in Direct_cmd to ' 2 ' b00 which makes DRAM controllers issue ' Precharge all ' memorycommand.

The value written is 0b00 and corresponds to:

3 and 4. Program Mem_cmd the Direct_cmd to ' 2 ' b01 which makes DRAM Controller issue ' AutoRefresh ' Memorycommand.

AutoRefresh writes the 0b01000000000000000000=0x40000, which can be seen and is correct.

5.Program mem_cmd to ' 2 ' B10 in Direct_cmd, which makes DRAM Controller issue ' MRS ' memory Command-bank address for EMRs m UST be set.

0X0A0000=0B10100000000000000000 can see that it was written to Direct_cmd 10.

6.Program mem_cmd to ' 2 ' B10 in Direct_cmd, which makes DRAM Controller issue ' MRS ' memory command.-Bank address for MRS m UST be set.

0x080032=0b10000000000000110010, you can see that it was written to Direct_cmd 10. The operation is also correct.

Here, Uboot memory initialization is complete, followed by the initialization of the storage controller:

5.Program memc_cmd to ' 3 ' b000 which makes DRAM Controller enter "Ready" state.

6.Check Memory Status field in Memc_stat until memory status becomes ' 2 ' bo1, which means ' ready '.

Mem. S

. text

. Global Mem_init

Mem_init:

Ldr R0, =0x7e00f120

mov r1, #0x8

STR R1, [R0]

LDR R0, =0x7e001004 @ Memory Control Command Register

mov r1, #0x4 @ According to the manual you need to enter the configuration mode first

STR R1, [R0]

LDR r0, =0x7e001010 @ Flush Register Address

LDR R1, = ((7800/(1000000000/133000000) + 1)) @ Set Refresh Time

STR R1, [R0]

Ldr R0, =0x7e001014 @CAS Latency Register

mov r1, # (3 << 1)

STR R1, [R0]

Ldr r0, =0x7e001018 @t_DQSS Register

mov r1, #0x1

STR R1, [R0]

Ldr r0, =0x7e00101c @T_MRD Register

mov r1, #0x2

STR R1, [R0]

Ldr r0, =0x7e001020 @t_RAS Register

LDR R1, = ((45/(1000000000/133000000) + 1))

STR R1, [R0]

Ldr r0, =0x7e001024 @t_RC Register

LDR R1, = ((68/(1000000000/133000000) + 1))

STR R1, [R0]

Ldr r0, =0x7e001028 @t_RCD Register

LDR R1, = ((23/(1000000000/133000000) + 1))

STR R1, [R0]

Ldr r0, =0x7e00102c @t_RFC Register

LDR R1, = ((80/(1000000000/133000000) + 1))

STR R1, [R0]

Ldr r0, =0x7e001030 @t_RP Register

LDR R1, = ((23/(1000000000/133000000) + 1))

STR R1, [R0]

Ldr r0, =0x7e001034 @t_rrd Register

LDR R1, = ((15/(1000000000/133000000) + 1))

STR R1, [R0]

Ldr r0, =0x7e001038 @t_wr Register

LDR R1, = ((15/(1000000000/133000000) + 1))

@ LDR R2, [R0]

STR R1, [R0]

Ldr r0, =0x7e00103c @t_wtr Register

mov r1, #0x07

STR R1, [R0]

Ldr r0, =0x7e001040 @t_xp Register

mov r1, #0x02

STR R1, [R0]

Ldr r0, =0x7e001044 @t_xsr Register

LDR R1, = ((120/(1000000000/133000000) + 1))

STR R1, [R0]

Ldr r0, =0x7e001048 @t_esr Register

LDR R1, = ((120/(1000000000/133000000) + 1))

STR R1, [R0]

LDR R0, =0x7e00100c @ Memory Control configuration Register

LDR R1, =0x00010012 @ Configuration Controller

STR R1, [R0]

Ldr R0, =0x7e00104c @32 bit DRAM configuration control register

LDR R1, =0x0b45

STR R1, [R0]

LDR R0, =0x7e001200 @ Chip selection Register

LDR R1, =0x150f8

STR R1, [R0]

LDR r0, =0x7e001304 @ User Configuration Register

mov r1, #0x0

STR R1, [R0]

Ldr R0, =0x7e001008

LDR R1, =0x000c0000

STR R1, [R0]

LDR R1, =0x00000000

STR R1, [R0]

LDR R1, =0x00040000

STR R1, [R0]

LDR R1, =0x000a0000

STR R1, [R0]

LDR R1, =0x00080032

STR R1, [R0]

Ldr R0, =0x7e001004

mov r1, #0x0

STR R1, [R0]

Check_dmc1_ready:

Ldr R0, =0x7e001000

LDR R1, [R0]

mov R2, #0x3

and R1, R1, R2

CMP R1, #0x1

BNE Check_dmc1_ready

Nop

mov pc, LR

31.6410 Knowledge of memory