8259A initialization Programming (RPM)

Within 8259A there are two sets of registers, one for the command register, for the initialization command word ICW1~ICW4 (initialization commands words) for the CPU write, and the other for the operation of the Command register, Operation command Word ocw1~ocw3 (Operation command words) for storing CPU writes.

1. Initialize the format of the command word ICW

When the address line A0 is 1 o'clock, 8259A provides 4 (ICW1~ICW4) initialization command words and prescribes strict initialization steps.

8259A is the core device of the interrupt system, and its initialization programming involves many problems of software and hardware that interrupt the system, and once initialization is completed, all hardware interrupt sources and interrupt handlers must be restricted.

(1) The format of ICW1 ICW1 is shown in format 6.12

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IC4 (ICW4 needed/no ICW4 needed): Indicates whether the command word ICW4 is required to be written at initialization time. In the 80X86 CPU system you need to define the ICW4, set the ic4=1.

SNGL (Single/cascade Mode): Indicates whether the 8259A uses monolithic or multi-slice cascading in the system. Sngl=1 is a single chip, sngl=0 is multi-slice cascade.

Analog Devices (call address interval): Sets the invocation interval, which is not valid in the 80486 CPU.

Ltim (Level/edge triggered mode): Defines how the interrupt request is triggered by the IRi . The ltim=1 is a level trigger and the ltim=0 is an edge trigger.

D4:ICW1 's flag, constant is 1.

D5~d7: Unused, usually set to 0.

(2) format of the ICW2

The ICW2 is used to set the interrupt type number, as shown in format 6.13.
　　　　　　　　　　　　　

The low 3-bit id2~id0 in the ICW2 is automatically introduced by the encoding of the interrupt request input IRi(i=0~7), and the high 5-bit t7~t3 is written by the user. If the ICW2 is written to 40H, the IR0~IR7 corresponding interrupt class model is 40h~47h.

(3) format of the ICW3

ICW3 is a cascading command word that needs to be written in cascade mode. The main film and the corresponding ICW3 from the film format, the main piece ICW3 format 6.14, shown in the format of the slice ICW3 6.15.

　　　　　　　　　　
Figure 6.14 Format of the main slice ICW3 6.15 from the format of the slice ICW3
S7~s0 corresponds to the IR7~IR0, if the main piece IRi(i=0~7) is connected from the chip on the pin, then si= 1, otherwise si= 0.

ID2~ID0 is the identification code from the chip to the main piece IRi . For example, ID2~ID0 should be set to 010,d7~d3 unused when the interrupt request signal int from the slice is connected to the IR2 of the main slice, typically set to 0.

In the interrupt response, the main slice through the Cascade signal Line CAS2~CAS0 send out the identity code of the allowed interrupt from the slice, each from the slice with their own ICW3 and cas2~cas0 comparison, the two consistent from the chip is determined as the current interrupt source, you can send the slave chip interrupt type code.

(4) format of the ICW4

The ICW4 is used to set the working mode of 8259A, which is shown in format 6.16.

　

MP (microprocessor): Sets the CPU mode. Mp=1 is 80x86 mode, Mp=0 is 8080/8085 mode.

AEOI (auto End of interrupt): Sets the break end mode for 8259A. Aeoi=1 is the auto-end mode, and Aeoi=0 is the non-auto-end mode.

(master/slave): Select the buffer cascade mode under the main slice with the slave slice. =1 is the main film, =0 is from the film.

BUF (buffer): Sets the buffering mode. The buf=1 is buffered and the buf=0 is non-buffered.

SFNM (special fully nested mode): Sets the special full nesting mode. Sfnm=1 is a special fully nested method, Sfnm=0 is a non-special complete nesting method

D7~d5: Undefined, usually set to 0.

Note: When more than 8259A cascade, if the 8259A data line and the system bus to join the bus driver, pin as a bus driver control signal, D3 bit buf should be set to 1, at this time the main slice and the distinction from the chip can not rely on the pin, but the origin of the choice, when the =0 when the main tablet. If buf=0, the definition is meaningless.

2. Format of the operation command Word OCW

The Operation command Word has OCW1, OCW2 and OCW3.

(1) format of the OCW1

OWC1 is the interrupt mask word, the Write Interrupt screen register (IMR), the external interrupt request signal IRi is shielded,

As shown in format 6.17.

　　　　　　　　　　　
Figure 6.17 Format of OCW1

When a bit mI(Interrupt mask) is 1 o'clock, then the corresponding IRi request is forbidden; when Mi is 0 o'clock, then the corresponding IRi request is allowed. can be written or read as needed at any time during work.

(2) format of the OCW2

The OWC2 is used to set the interrupt priority mode and break end mode, as shown in format 6.18.

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L2~l0 (IR level to be acted upon): 8 Interrupt Request input IR7~IR0 flag bit, used to specify the interrupt level. L2~L0 Specifies whether the interrupt level is valid and is controlled by the SL (specific levels) bit. The L2~L0 definition is valid when sl=1, and the l2~l0 definition is invalid when sl=0.

EOI (end of interrupt): Break End command. If Eoi=1, the interrupt service subroutine ends at the end of the 8259A loopback interrupt end command EOI, in order to make the Interrupt service register (ISR) the highest priority in the current reset (normal EOI mode), or by the l2~l0 of the priority of the throne reset (special EOI mode).

R (rotation): Sets the priority loop mode bit. The r=1 is the priority automatic circulation mode; The r=0 is the priority fixed mode. D4, D3 is the OCW2 flag bit.

(3) format of the OCW3

The OCW3 is used to set or clear the status of special shielding and read registers, as shown in format 6.19.

RR (read register command): Read ISR and IRR command bit, RIS (read interrupt register Select) Read register select bit. When Rr=1,ris=0, read the IRR command, and when Rr=1,ris=1, read the ISR command. When performing a read ISR or IRR operation, the Read command OCW3 is written, followed by instructions to read the ISR or IRR.

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For example, two ports with 8259A addresses are 20H and 21H,OCW3, and ISR and IRR share an address of 20H.
The program that reads the ISR content

MOV AL, 00001011B
Out 20H, AL; Read ISR command write OCW3
In AL, 20H; Read the ISR content to AL in the program that reads the IRR content
MOV AL, 00001010B
Out 20H, AL; Read the IRR command to write OCW3
In AL, 20H; Read the IRR content to Al

P (Poll command): Queries the bit for the interrupt status. When P=1, you can read the contents of the status register to see if an interrupt request is being processed, and if so, give the highest priority of the current processing interrupt. The interrupt status is shown in register 6.20.

　　　　　　　　　　

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When reading the interrupt state Word, write the interrupt query command first, then read the interrupt status word, the program is as follows:

MOV AL, 00001111B
Out 20H, AL; Read interrupt status Word command write OCW3
In AL, 20H; Read Interrupt status Word

The combination of ESMM (enable special mask mode) and SMM (special mask mode) can be used to set or remove special shielding methods. When Esmm=1,smm=1, special shielding is set; when esmm=1,smm=0, special shielding is removed.

3. Initialization of 8259A programming

The initialization programming of 8259A needs to be written to the initialization command word ICW1~ICW4, which can be set for its connection mode, interrupt triggering mode and interrupt ending mode. However, since ICW1~ICW4 uses two port addresses, that is, ICW1 with a0=0 ports, ICW2~ICW4 uses a0=1 ports, so the initialization program should be written in strict accordance with the system, that is, write ICW1 first, then ICW2, ICW3, ICW4.

The initialization process for 8259A is shown in 6.21.

The Operation command Word OCW1~OCW3 is more flexible, has no fixed format, can be written in the main program, or can be written in the interrupt service subroutine, depending on the need. Here's an example of how to write a 8259A initialization program.
　　　　　　　　　　　　

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"Example 6.1" a microcomputer system using the master, from the two 8259A management interrupt, from the chip interrupt request int and the main slice of the IR2 connection. The main chip works in a special completely nested, non-buffered and non-automatic end mode, the interrupt class model is 40H, the port address is 20H and 21H. The interrupt class model is 70H and the port address is 80H and 81H, since the slice works in a fully nested, non-buffered, and non-automatic end mode. Try to write the main slice and the initialization program from the slice.

According to test instructions, write the ICW1, ICW2, ICW3, and ICW4 formats, written in the order shown in Figure 6.21. Write the initialization program as follows:

The initialization procedure for the main slice 8259A is as follows:

MOV AL, 00010001B; Cascade, edge Trigger, need to write ICW4
Out 20H, AL; Write ICW1
MOV AL, 01000000B; Interrupt class Model 40H
Out 21H, AL; Write ICW2
MOV AL, 00000100B; The IR2 pin of the main piece is connected from the chip
Out 21H, AL; Write ICW3
MOV AL, 00010001B; Special fully nested, unbuffered, auto-end
Out 21H, AL; Write ICW4

The initialization program from the slice 8259A is as follows:

MOV AL, 00010001B; Cascade, edge Trigger, need to write ICW4
Out 80H, AL; Write ICW1
MOV AL, 01110000B; Interrupt class Model 70H
Out 81H, AL; Write ICW2
MOV AL, 00000010B; The IR2 pin of the main piece
Out 81H, AL; Write ICW3
MOV AL, 00000001B; Fully nested, non-buffered, non-automatic end
Out 81H, AL; Write ICW4

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8259A initialization Programming (RPM)