Allegro platform can run in Linux

Article Title: Allegro platform can run on Linux. Linux is a technology channel of the IT lab in China. Includes basic categories such as desktop applications, Linux system management, kernel research, embedded systems, and open source.
Cadence design systems will launch a platform named Allegro that can model high-speed Interconnection from IC to encapsulation and encapsulation to printed circuit boards in the entire system. Allegro includes existing PCB and encapsulation tools of Cadence and adds two new packaging tools. In addition, it allows different chip, encapsulation, and PCB design teams to work with the same System Interconnection model. Users of the platform will be able to track a signal from the I/O buffer of the IC through the redistribution layer until it passes through the protruding pad of the bare chip, the encapsulated base, and the connector to the PCB.
　　
"The Allegro platform provides all the technologies required to design these interconnections and supports the methodologies required to complete such tasks ." Said Jamie Metcalfe, vice president of strategic marketing, silicon-encapsulation-circuit board business department, Cadence.
　　
Today, different design groups are often separated at work. These teams usually receive draft specifications in the spreadsheet format from the System Architect and then work hard to design their respective System Interconnect sections, Metcalfe said.
　　
So far, no feasible technology has been available in the industry to allow architects to model the interconnection across all structures and allow different interconnection designers to communicate with each other to make the best choice through trade-offs. Early Cadence tools allow encapsulation and PCB designers to monitor signal integrity and timing issues from the circuit board to the encapsulation, but they cannot design and analyze the interconnection from the IC to the encapsulation. The emergence of Allegro has changed this situation.
　　
Currently, two tools that can be authorized externally are Allegro Package Designer and Allegro Package SI. The System Architect can use Package Designer to create a new type of model that describes the connection throughout the entire process.
　　
This virtual System Interconnection (VSIC) model captures the intent of the design team in terms of system interconnection or rough layout, and then the model is passed to circuit designers, encapsulation designers, and PCB designers, each type of designer implements a part of the system while taking into account the entire interconnection.
　　
The VSIC model generally contains the behavior description and Constraint Topology of the I/O buffer. "For example, We can insert a topology that tells the system that a special interconnect must be implemented in the form of a differential pair and must work on a 24 inch FR-4 material and terminate in a particular way." Metcalfe said.
　　
The VSIC model also contains the underlying planning guide for critical signal segments. "Designers can use these guidelines as constraints when implementing the design of their respective parts or simulating the behavior of buffers and interconnections ." Metcalfe.
　　
In this methodology, I/O buffer designers can use Cadence's so-called Oso tool. In addition, designers can use the Allegro Package Designer and Allegro Package SI to design the burst array, use the Allegro Packaging tool to design the encapsulation, and use the Allegro PCB tool to design the circuit board. The design team can refer to the VSIC model when designing their respective interconnect sections and continue to improve the model. However, any part of the model can be "locked" to prevent changes, Metcalfe adds.
　　
"Beta testing shows that using the Allegro platform and its methodology can reduce the system design cycle by 8 to 12 weeks," Metcalfe claims. "Allegro can also cut packaging costs by up to 66% ." The platform and methodology support plug-ins of the dedicated chip design suite.
　　
Allegro platform can run on Windows, Sun Solaris, HP-UX, ibm aix, and Red Hat Linux. The annual license fee for Allegro Package Designer and Package SI starts at $54 thousand and $45 thousand respectively. The PCI Express chip design kit used with Allegro pcb si can be downloaded free of charge from www.allegroSI.com.