Arm instruction machine code and case analysis

First, the previous image is the same:

[28:31] cond:
Code of command execution Condition
[26:27]: Reserved
[25] X: determines whether to adopt "instant addressing (set to 1)" or "register addressing (set to 0 )"
[] Opcode: the encoding of operators (such as mov and LDR)
[20] s: the embodiment of the S Mark in the instruction, with S, the bit is 0, without s, is 1
[16: 19] rn: set to zero.
[] RD: the encoding of the target register. In ARM9. each mode has 16 General registers.
[0: 11] shifter-operand: the operand of the command (immediate number or register, etc)

Analyze machine code 0xfca0f001

Binary: 11111100101000001111000000000001

[31: 28]: 1111
[27:26]: 11
[25]: 0
[]: 0101
[20]: 0
[]: 0000
[]: 1111
[]: 000000000001

(To be continued)

Refer:

Http://blog.csdn.net/gooogleman/article/details/3758555

Http://sjdai.spaces.eepw.com.cn/articles/article/item/76690