Arm working mode

Original: http://www.cnblogs.com/zzx1045917067/archive/2012/11/26/2789736.html

Description: This article is based on the original text slightly changed.

First, the basic concept

The ARM architecture considers memory as a linear combination of bytes starting from a zero address. Place the first stored word (32-bit) data from 0 bytes to three bytes, placing the second stored Word data from the fourth byte to the seventh byte, one at a time.

As a 32-bit microprocessor, the ARM architecture supports a maximum addressable space of 4GB.

The arm microprocessor has two working states, one arm and one thumb.

Where the ARM state processor performs 32-bit word-aligned arm instructions; Thumb state: The processor performs a 16-bit, half-word aligned thumb instruction.

During the process of running the program, you can convert between the two states in a corresponding way. Changes in the processor's operating state do not affect the processor's operating mode and the contents of the corresponding registers.

Two or seven modes of operation

1, User mode (USR): For the normal execution of the program;

2, fast interrupt mode (FIQ): For high-speed data transmission;

3, external interrupt mode (IRQ): For the usual interrupt processing;

4. Management Mode (SVC): The protection mode used by the operating system;

5. Data access termination mode (ABT): Enter this mode when data or instruction Prefetch terminates, can be used for virtual storage and storage protection;

6, System mode (SYS): Run a privileged operating system task;

7. No instruction Abort mode defined (und): Enter this mode when undefined instruction is executed and can be used to support hardware.

There are two ways to switch between arm's working mode:

Passive switching: Generates some exceptions or interrupts during arm operation to automate mode switching

Active switching: Through the software change, that is, the software Settings register to switch the mode of the arm, the operating mode of the arm can be the corresponding register of the assignment to switch.

In addition to user mode, the remaining 6 modes of operation are privileged mode; most programs run in user mode, and some protected system resources cannot be accessed while the processor is running in user mode.

The remaining 5 modes in privileged mode, except for the system mode, are called exception modes;

Access to privileged mode is to handle interrupts, exceptions, or access to protected system resources;

Third, register

1) 37 Registers

ARM has 31 general-purpose 32-bit registers plus 6 program status registers. Some registers are shared for all work modes, and some are specifically for a certain mode of operation.

r13--stack pointer register for holding stack pointers;

r14--Program Connection Register, when the implementation of the BL subroutine call instruction, R14 get R15 backup, and when an interrupt or an exception occurs, R14 save the return value of R15;

r15--program counter;

The fast interrupt mode has 7 backup registers R8-r14, which makes it possible to perform most programs in fast interrupt mode without even having to save any registers;

Other privileged modes contain two separate register copies of R13, R14, which allow each mode to have its own stack pointer and connection register;

2) Current program status register (CPSR)

The meanings of CPSR are as follows:

T-bit: 1--CPU in thumb State, 0--cpu in arm state;

I, F (interrupt prohibit bit): The first stop interruption, 0--interrupt enable;

Operating mode bit: Can change these bits, make mode switch; 3) program Status Save Register (SPSR)

When switching into a privileged mode, SPSR saves the CPSR value of the previous working mode, so that when the previous working mode is returned, the value of SPSR can be restored to CPSR;

Four, mode switch

When an exception occurs and the CPU enters the appropriate exception mode, the following work is done automatically by the CPU:

1, in the abnormal mode of R14 Save the previous operation mode of the next command to execute the address;

2. Copy the value of CPSR into the spsr of abnormal mode;

3, the working mode of the CPSR is set to the working mode corresponding to the abnormal mode;

4, so that the PC value is equal to the exception mode in the exception vector table address, that is, jump to execute the exception vector table corresponding instructions;

When you return from the abnormal mode of operation to the previous mode of operation, the following work needs to be done by the software:

1, the abnormal mode R14 minus an appropriate value (4 or 8) after the assignment to the PC Register;

2. Assign the value of the exception mode SPSR to CPSR.