Armv8 architecture learning --- privilege, security, modes and exception levels

1. Runs 64-bit registers and is compatible with the armv7 architecture software. That is, it supports both 32bit and 64bit, aarch64 & aarch32

2. the privilege and mode are separated, and armv7 is integrated.

In armv8, there are pl3, PL1, pl0, and no pl2 in the security status, and the safe memory space can be accessed.

In the unsafe state, there are pl2, PL1, pl0, and no pl3, and the safe memory space is not accessible.

Each PL level determines a set of commands and registers.

3. Exception levels (EL)

There are also four levels of El, el0, el1, EL2 (only in non-secure State), and EL3 (only in secure State)

In aarch64, El decides pl. The current execution is in elx, and PL is PLX.

El switching: an exception or an exception is returned from an exception.

An exception occurred: El> = current El

Returned from an exception: El <= current El

El determines the current execution status, such as the register, PL, and register bit width.

El level: the larger the number, the higher the level, the larger the permission.

Generally, el0 is used for applications, el1 is used for OS kernels, EL2 is used for hypervisor, and EL3 is used for security monitoe.

4. Register Bit Width

The El level increases, and the Register bit width increases or remains unchanged. The El level decreases, and the Register bit width decreases or remains unchanged.

The register Bit Width of el0 is determined by a bit in the HCR/scr register of el1. It can only be set by returning an exception.

The register Bit Width of el1 is determined by the HCR register in EL2 or a bit in the SCR register in EL3, and whether it is EL3 or el2.

The register Bit Width of EL2 and EL3, which is set by the configuration pin during reset.

5. Instruction Set

A32: compatible with the 32bit arm Instruction Set in armv7 Architecture

T32: compatible with the 16bit & 32bit thumb Instruction Set in armv7 Architecture

T32ee: compatible with the 16bit & 32bit thumbee Instruction Set in armv7 Architecture

A63: armv8's new 64-bit Instruction Set

6. aarch32

If the highest level El such as el2orel3 uses aarch32, the entire system must use aarch32;

In aarch32, the execution in armv8 is the same as that in armv7, but the virtualization extension and physical address expansion (lpae) are somewhat changed.

7. Abnormal Return status

In aarch64, the returned exception status is determined by the ELR (exception link register) and spsr (saved processor State Register) registers.

ELR saves the exception return address, and spsr saves the processor status.

8. Stack pointer Selection

In el0, the stack pointer is sp_el0, and the others are sp_elx.

9. Security Model

In armv7, Security Extension introduces the monitor mode, which enables switching between security and non-security states.

In armv8, when EL3 uses aarch32, to be compatible with armv7, there is only one el3.

Non-secure state

El0 Application

El1 OS

EL2 hypervisor

EL3 secure Monitor-> secure OS-> Secure Application

In armv8, when EL3 uses aarch64, El and security are separated

Non-secure state

El0 application Secure Application

El1 OS secure OS

EL2 hypervisor

EL3 secure Monitor

10. Execution Mode

The modes in armv7 include user, Fiq, IRQ, supervisor, monitor, abort, Hyp, undefined, and system.

The modes of armv8 in aarch64 are el0t, el1t & el1h, el2t & el2h, el3t & el3h. The suffix t indicates sp_el0 Stack pointer, and h indicates sp_elx Stack pointer.

 

Armv8 architecture learning --- privilege, security, modes and exception levels