Assembly write startup code open Icache

"Teacher Zhu's IoT lecture" study notes

Study Address: www.zhulaoshi.org

The first two sections of the teacher said a word, I forgot to write up, today to fill.

SoCs are basically read-write control of peripherals through similar gpio, memory controllers, and so on.

There are also special, like the watchdog, there is no peripherals corresponding to it.

Okay, let's start with our theme for today, Icache.

So, what is Icache?

It is a kind of memory, although it currently touches several kinds of memory, registers, DDR, and so on, they work in the physical principle although different, but the access properties are very similar.

On the speed

CPU > Register > Cache > DDR

On the capacity

CPU < Register < Cache < DDR

In the whole system, the CPU supply chain consists of: Register +cache+ddr+ HDD/flash four order.

210 internal 32KB Icache and 32KB Dcache (see CPU core 32KB/32KB i/d cache 800mhz/1ghz)

Icache is used to cache instructions,

Dcache is used to cache data, the bare metal part is not available, the operating system MMU.

CPU design has a rationale: When the old code executes, the next sentence is much more likely to execute the code next to the current line of code.

If not, you need to clean up the old cache and reload the new cache.

At present, everything in Icache is automatic and does not require us to do anything.

We just need to open or close icache.

The BL0 in Irom has opened the Icache. (Step two: Initialize the instruction Cache)

So how do we set it up? Have you ever thought about the coprocessor that was mentioned before the assembly instruction ~

Here we are using the CP15 coprocessor to control the Icache.

Assembly code Read-write CP15 with switch Icache

	MRC p15,0,r0,c1,c0,0//			read out CP15 C1 to r0
	Bic r0, R0, # (1<<12)			//bit12 0  off Icache
	Orr R0, R0, # (1 <<12)			//bit12 1  open Icache
	mcr p15,0,r0,c1,c0,0;

With the switch Icache, you can see that the speed of the light flashes will change in the LED experiment.