Asynchronous reset Synchronous Release

Advantages and disadvantages of synchronous reset and asynchronous reset

Advantages of Synchronous Reset:

• It is generally possible to ensure that the circuit is fully synchronized.
• Ensure that the reset occurs only on the effective clock edge and can be used as a means of filtering out burrs.

Disadvantages of Synchronous Reset:

• The effective duration of the reset signal must be greater than the clock cycle to truly be recognized by the system and the reset is complete. At the same time, such as: Clock offset, combined logical path delay, reset delay and other factors.
• Because most of the manufacturers in the target database triggers are only asynchronous reset port, with synchronous reset, it will consume more logical resources.

Advantages of Asynchronous Reset:

• The asynchronous reset signal is easy to identify and can be easily used for global reset.
• Logical resources can be saved because the triggers in most vendor target libraries have asynchronous reset ports.

Async Reset Disadvantage:

• Reset signals are susceptible to burrs.
• When the reset end moment is in the metastable window, it is not possible to determine whether the current reset state is 1 or 0, which results in metastable state.
• Asynchronous reset Synchronous Release

  The above disadvantages can be eliminated by using asynchronous reset synchronous release. The so-called asynchronous reset, synchronous release is when the reset signal arrives not by the clock signal synchronization, but when the reset signal is released by the clock signal synchronization. The schematic and code for asynchronous reset synchronous release are as follows:
  

• //Synchronized Asynchronous ResetModuleSync_async_reset (inputClock,inputReset_n,inputData_a,inputData_b,OutputOut_a,Outputout_b); RegREG1, REG2; RegReg3, REG4; AssignOut_a =REG1; AssignOut_b =REG2; AssignRst_n =REG4;  always@ (PosedgeClockNegedgeReset_n)begin            if(!reset_n)beginreg3<=1'B0;REG4 <=1'B0;            End            Else beginreg3<=1'B1;REG4 <=reg3; End        End                 always@ (PosedgeClockNegedgeRst_n)begin            if(!rst_n)beginREG1<=1'B0;REG2 <=1'B0;            End            Else beginREG1<=data_a; REG2<=Data_b; End        EndEndmodule  //Sync_async_reset

Asynchronous reset Synchronous Release