BCD Code Encoder _ Step-shift Method

September 14, 2016
Author: dengshuai_super
Source: http://blog.csdn.net/dengshuai_super/article/details/52541402
Disclaimer: Please specify the author and source of the reprint.

BCD encoder (BINARY-BCD Converter) _ Step-shift Method

Gradually left shift, when the BCD0 moved to 11 o'clock equals 3<4, no adjustment;
When BCD0 is moved to 111 equals 7>4, plus 3 equals 10, the corresponding binary is 1010;
Once again shifted, BCD1 is 1,bcd0 0101 equals 5>4, plus 3 equals 8 corresponding binary is 1000;
Shift again, bcd1=11,bcd0=0001,bin=11, because BCD1 and BCD0 are <4, so do not operate;
Again shift, Bcd1=110,bcd0=0011,bin=1, because Bcd1=6>4, plus 3 is equal to 9, corresponding to the binary system 1001, at this time bcd1=1001,bcd0=0011,bin=1;
Last Shift: bcd2=1,bcd1=0010,bcd0=0111.

Module BINARY_TO_BCD (clk_i, Ce_i, Rst_i, Start_i, Dat_binary_i, Dat_bcd_o, done_o); Parameter bits_in_pp = 16;  # of bits of binary input parameter bcd_digits_out_pp = 5;  # of digits of BCD output parameter bit_count_width_pp = 4;                      Width of bit counter//I/O declarations input clk_i;                       Clock signal input ce_i;                      Clock enable input input rst_i;                    synchronous reset input start_i;        initiates a conversion input [bits_in_pp-1:0] dat_binary_i;  Input bus output [4*bcd_digits_out_pp-1:0] dat_bcd_o;                     Output bus output done_o;

Indicates conversion is do reg [4*bcd_digits_out_pp-1:0] dat_bcd_o;
Internal signal Declarations reg [bits_in_pp-1:0] Bin_reg;
reg [4*bcd_digits_out_pp-1:0] Bcd_reg;
Wire [bits_in_pp-1:0] bin_next;
reg [4*bcd_digits_out_pp-1:0] bcd_next;
Reg Busy_bit;
reg [bit_count_width_pp-1:0] bit_count; Wire Bit_count_done; --------------------------------------------------------------------------//Functions & Tasks/-----------
  ---------------------------------------------------------------function [4*bcd_digits_out_pp-1:0] BCD_ASL;
  input [4*bcd_digits_out_pp-1:0] din;
  Input newbit;
  Integer k;
  Reg CIN;
  reg [3:0] digit;
  reg [3:0] digit_less;
    Begin cin = Newbit;
      for (k=0; k<bcd_digits_out_pp; k=k+1) begin digit[3] = din[4*k+3];
      DIGIT[2] = din[4*k+2];
      DIGIT[1] = din[4*k+1];
      Digit[0] = Din[4*k];
      digit_less = digit-5;
        if (Digit > 4 ' b0100) begin bcd_asl[4*k+3] = digit_less[2];
        BCD_ASL[4*K+2] = digit_less[1];
        BCD_ASL[4*K+1] = digit_less[0];
        BCD_ASL[4*K+0] = cin;
      cin = 1 ' B1;
        End ELSE begin bcd_asl[4*k+3] = digit[2];
        BCD_ASL[4*K+2] = digit[1];
        BCD_ASL[4*K+1] = digit[0];
        BCD_ASL[4*K+0] = cin;
      cin = 1 ' b0;

End    End//end of For loop end endfunction//-------------------------------------------------------------------------- Module Code//--------------------------------------------------------------------------//Perform Proper
Shifting, binary ASL and BCD ASL Assign Bin_next = {bin_reg,1 ' B0};
Always @ (Bcd_reg or bin_reg) begin Bcd_next <= BCD_ASL (bcd_reg,bin_reg[bits_in_pp-1]);  End//Busy bit, input and output registers always @ (Posedge clk_i) begin if (rst_i) begin busy_bit <= 0;
  Synchronous reset Dat_bcd_o <= 0;
    End else if (start_i && ~busy_bit) begin busy_bit <= 1;
    Bin_reg <= dat_binary_i;
  Bcd_reg <= 0;
    End else if (busy_bit && ce_i && bit_count_done && ~start_i) begin busy_bit <= 0;
  Dat_bcd_o <= Bcd_next;
    End else if (busy_bit && ce_i && ~bit_count_done) begin Bcd_reg <= Bcd_next;
  Bin_reg <= Bin_next; End End Assign done_o = ~busy_bit;
  Bit counter always @ (Posedge clk_i) begin if (~busy_bit) bit_count <= 0;
else if (ce_i && ~bit_count_done) bit_count <= Bit_count + 1;

End Assign Bit_count_done = (Bit_count = = (bits_in_pp-1)); Endmodule

Source:
https://ke.qq.com/user/tasks/index.html?cid=117307#tid=100127911&fr=2