Cadence power integrity simulation practice (1)

Software: Cadence 16.5

Tool used: Allegro pcb pi option XL power integrity

Use resources: simulation instance: http://download.csdn.net/detail/wu20093346/7660995

Simulation purpose: to select a decoupling Capacitor Based on the simulation results of a single node, so that the PCB can meet the set target impedance.

1. Create a New PCB File

Open Allegro pcb pi option XL:

Create a new board, enter the name pi_allegro, and set the English path.

2. Start the power integrity setting Wizard:

Execute analyze-> power integrity

Click OK to close the signoise errors/warnings window. The power integrity setting wizard window appears.

Click next, and then import the PCB border. This is faster. You don't have to draw any more. The instance is available in the resource.

Click Import outline and select lab2.brd from the resource.

Next, import the stack structure. Next, click Import stack-up, and select lab2.brd.

Click Next to enter the DC network and plane Association Settings dialog box. The information has been imported, and then click Next.

The power pair setup dialog box appears. Set the power pair

Select S1 for plane1, S2 for plane2, and Add. Repeat this step.

Select S3 for plane1, S4 for plane2, and add

Select S5 for plane1, S6 for plane2, and add

Three power pairs are added,

Click Next. At this time, the dialog box does not display any components, because this is a new PCB and no components have been placed.

Click Next

Select DCL library and click Next to enter library setup

On Power plane pair, select the flat pair for the S1-S2 and click the capacitor library C:/Cadence/spb_16.5/share/PCB/pcb_lib/npo_0603_caps

Select cap_npo_0603_10u

On Power plane pair, select the flat pair for the S3-S4 and click the capacitor library C:/Cadence/spb_16.5/share/PCB/pcb_lib/npo_0603_caps

Select cap_npo_0603_6_8u

On Power plane pair, select the flat pair for the S5-S6 and click the capacitor library C:/Cadence/spb_16.5/share/PCB/pcb_lib/npo_0603_caps

Select cap_npo_0603_8_2u

3. Set simulation parameters

Select the S1-S2 in the power plane pair bar, select 5% in the ripple tolerance volatility margin bar, and enter 5 in Max Delta current, then the dialog box displays the current target impedance as 30 m².

Select the S3-S4 in the power plane pair bar, select 5% in the ripple tolerance volatility margin bar, and enter 5 in Max Delta current, then the dialog box displays the current target impedance as 30 m².

Select the S5-S6 in the power plane pair bar, select 5% in the ripple tolerance volatility margin bar, and enter 5 in Max Delta current, then the dialog box displays the current target impedance as 20 millons.

Change the default Mount Inductance Value, click the control button in the dialog box, click the mounted inductance option in power Integrity Control, enter 225ph in default mounted inductance, and click OK.


The voltage adjustment module is placed, and a voltage adjustment module must be placed on each individual plane pair for single-node simulation. Select S5-S6, click VRM edit, OK, put VRM


Select S3-S4, S1-S2, place VRM in the same steps
4. Single Node simulation select S1-S2, click Single Node simulation, the sigwave window appears
Select the S3-S4, click Single Node simulation, and the display is:
Select the S5-S6, click Single Node simulation, and the display is:


Analyze these three response curves, because the plane interval of the S3-S4 plane pair (23.32504 mils) is larger than the plane interval of the S1-S2 plane pair 0.5mils, a plane with a large plane interval produces a smaller capacitance, so it has a higher impedance response curve. The plane of the S1-S2 is very close to the response curve of the S5-S6, because the two plane pairs have close areas and almost equal capacitance values between the plane. The impedance response curves with capacitors are different because each plane pair was previously assigned a different capacitance value, which has different resonance frequencies and different equivalent series resistance values.

Cadence power integrity simulation practice (1)