Chapter 2 don't forget me -- SignalTap II Logic Analyzer

I. Don't forget me.

The embedded logic analyzer sigbaltap II is an embedded logic analyzer that comes with Altera Quartus II. It differs from the Modelsim software simulation. It is an on-line simulation that allows you to more accurately observe data changes and facilitate debugging.

Many children who have learned single-chip microcomputer think that single-chip microcomputer can be debugged in one step online, while FPGA is concurrent and cannot be debugged in one step, which makes FPGA debugging difficult. In fact, this statement is not completely correct. Don't forget, there is also SignalTap II logic analyzer. With this embedded logic analyzer, debugging multi-channel or single-channel data, data sampling, monitoring, and other operations bring us great convenience. Therefore, FPGA Learning, using JTAG to debug siganltap II will be of great help.

II. Application Instances

In this example, the application of SignalTap II logic analyzer is briefly described based on the sine wave, triangle wave, sawtooth wave, and square wave waveform data. The steps are as follows:

(1) create a project and DesignCode, Pin configuration, RTL diagram as follows

(2) create a SignalTap II file

(3) set the signal name to be tested

(4) double-click the node to add the digital signal to be observed. Do not call the system clock, because this example uses the system clock as the sampling clock of the logic analyzer.

(5) Add the system sampling clock (similar to the oscilloscope sampling)

(6) set the sampling depth: Because the ESB/m9k is used, the sampling depth should be smaller than 9 KB. Here it is set to 2 kb.

(7) set the trigger position for sampling: trigger the hop-on-hop

(8) trigger method:

(I am not very clear here, probably in various modes)

(9) set the trigger input: select the trigger signal and trigger mode. Flag is used to trigger the enable signal, which is useless in actual engineering. It is only the enable signal of SignalTap II. For High-Level Trigger, the settings are as follows:

Note: The flag is the edge sampling signal. When the flag changes, it happens that the warm_data is in the steady state, so the flag is used as the sampling trigger. Of course, when the request is low, flag can also be omitted, and siganltap II will automatically sample according to a certain frequency.

(10) Save and yes, re-compile, and bind with this project to download to device (you can also set it in settings); For pin, if there is no logic analyzer test and no signal input, if you are too lazy to set it, You can not allocate out signals, but the CLK and rst_n must be allocated because it is the system drive signal.

(11) set handware setup and link to Device

(12) download the sof file (of course, you can also directly download it in q ii)

(13) process-anturon analysis, automatic analysis

(14) observe the output signal and set it to a analog signal.

(15) Why is it so handsome ....

(16) A bug may occur after the actual test for a period of time. It may be that the logic edge cannot be aligned for a long period of sampling. After all, it is not so perfect. Just reset it.

(17) after the test is OK, disable enable SignalTap II logic analyzer to reduce the logical unit and streamline the cost design:

(17) OK, in vain, just try, try, try ....