Concurrency and Locks

Concurrency and Locks

JUC AQS

AQS Overall structure

The acquisition process of locks

• The problem of CAS rote rotation number

Get the process of failure pending

The process of releasing the lock wakeup wait

• How to prevent loss of wake-up

  The team can not "snooze", find reliable waiting and let him wake himself up, not in order to acquire locks, all other situations tell the mark precursor don't forget to wake yourself up

  That's enough, apparently not. Check and sleep are clearly not an atomic operation for satisfying yourself to "sleep" conditions. No one wakes up after check and before "sleep" if conditions change

  Unpark and park have long prevented the problem, guessing that there are variables inside to remember the last post-operation state, while the operating system-supplied lock guarantees atomicity

• How to prevent surprise group problem

  The wake of a lock is usually the wake-up of a waiting thread and the wake-up of all waiting threads, usually under programming conditions if you want to reduce all wake-up caused by unnecessary competition, pay attention to the false

  Wake-up problem, wake-up thread if the condition does not meet the condition to release the lock and cause the wake chain to disconnect. It is not easy to wake the other waiting by releasing the lock.

  So for example, in Leader-follower mode, if the leader thread wakes any of the waiting threads only when the original leader thread leaves, then when the thread is in follower mode

  Because there is no wake-up in the state of downtime, so every time when the work is done to try to leader. If leader calls all other threads at the time of departure, it is obvious that the group is startled.

Aqs Summary

• Simple optimization of double check lock

• Rumor: CAS+CLH queues are semantically equivalent to locks

  The closure of a thread blocking wake is not sufficient, and it is necessary to ensure the atomicity of the scheduling switch with the shield interrupt and the forbidden preemption in the CPU instruction.

From CAs to memory barrier to cache consistency protocol

• Volatile Happens-before

  If a thread writes a new value first, the B thread is immediately followed by a clock cycle, which allows the command to empty the store buffer regardless of the lock prefix

  And the failure of the other processor to execute the cache, or the clock interrupt causes the store buffer to empty and then trigger the cache consistency synchronization) to read can

  Up-to-date value, but due to the need to interval a clock cycle, appears to violate Happens-before;

  During the cycle because lock triggers the cache consistency synchronization will invalidate the old value of the data item so there is no problem, the indirect triggering of the clock interrupt cache synchronization is similar.

• Unsafe source Code

Https://github.com/dmlloyd/openjdk/blob/jdk/jdk/src/hotspot/share/prims/unsafe.cpp

• CAS instruction and Bus lock cmpxchg16b

• Memory barrier and Cache consistency protocol

• Compiler optimizations, CPU scrambling execution "about architectures that are only for x86-64 other chaotic degrees of freedom are not considered, the principle is expected to be similar"

Adventure:

Data Adventures
Structural Adventures
Control Adventure (Branch adventure)
MESI, MOSI, Mesif

A picture beats thousand words (to be added),

Hardware structure: Write cache read priority with L1cache, write merge WC optimization; write back cache wb, write through cache wt,

Write fail WI, experience indicates write invalidation, more bandwidth savings

Write update Wu, looks fast, sometimes unnecessary if updating each cache is much more expensive than a failed instruction;

The update may be intermittent multiple times and expire once, and the cache row content is larger than the cache address size

X86-64 consistency is high, loadload Memory barrier is because the read barrier will force wait for invalidate queue to be emptied before continuing execution,

This eliminates the problem of the read order caused by it.

• The Cache consistency protocol provides the necessary means and mechanisms for cache consistency, and the memory barrier is through simple suppression of chaos and the use of these means and mechanisms

  Thus achieving a consistent external performance of the cache. Here the hardware of the external complexity of the isolation package, external exposure to a simple interface, internal implementation like the surface of the

  Iceberg.

The cache consistency protocol obviously has a locking semantics on the hardware.

Loadload

Loadstore

Storeload (x86 TSO's only chaotic place)

Storestore

Synchronized

• Object Header

• Lock escalation

• Safety Point and extension

  Accurate GC, secure point scheduling, and co-scheduling Java and Golang

Futex

Futex是一种用户态和内核态混合的同步机制。首先，同步的进程间通过mmap共享一段内存，futex变量就位于这段共享 的内存中且操作是原子的，当进程尝试进入互斥区或者退出互斥区的时候，先去查看共享内存中的futex变量，如果没有竞争发生，则只修改futex,而不 用再执行系统调用了。当通过访问futex变量告诉进程有竞争发生，则还是得执行系统调用去完成相应的处理(wait 或者 wake up)。简单的说，futex就是通过在用户态的检查，（motivation）如果了解到没有竞争就不用陷入内核了，大大提高了low-contention时候的效率。 Linux从2.5.7开始支持Futex。

• Spin lock

  One of the basic locks of the kernel

• Spin optimization (JDK9 and spin tips)

Spin is a constant retry of the value of the condition variable in the loop, which requires constant synchronization of the cache in order to ensure visibility, causing a lot of unnecessary overhead.

• RCU Lock

  The data contained is usually a pointer type, and each kernel has a dispatch indicating that if the other kernel is in the Read critical section of the RCU lock, after a round of dispatch (read critical section is not preempted)

  If there are new threads, the visible data is new and the old version can be released. If the RCU is preempted, a counter needs to be maintained at the beginning of the lock and at the end of the release.

• Shielded interrupts and no preemption

Elements of a lock

>cas>等待队列>屏蔽中断禁止抢占的原子调度上下文的切换

Understanding and experience

• If you don't prepare, you will draw your sword si gu your heart is vacant

• Read/write Timing

• The equivalence of control flow and data flow

• Several concurrent models actor, CSP, CPS/CALLCC

• The essence of the lock is the timing problem, scheduling can solve the timing problem, scheduling problem from the CPU point of view is the implementation of the problem, the lock is to protect the data, the lock is to restrict the execution of code to protect the data.

Mesi why is it possible to ensure consistency in distributed environment cache consistency?

First, the bus is huge, and he guarantees cache consistency across multicore and even multiple CPUs.

Because there is no unified bus in distributed environment, the coordinated control of convergence is absent.