Configuration space of PCI and PCI-E devices in PowerPC

PCI bus specifies the bus transaction that accesses the configuration space, which is called the configuration read/write transaction. Unlike the storage access transactions that use the storage address for access, the idnumber is used for addressing access to the PCI configuration space.

The ID of a PCI device consists of the bus number, device number, and function number.

For Embedded PowerPC applications, the PCI design is often very simple. The PCI bus is directly derived from the host Main Bridge on the CPU. Generally, there is no multi-level PCI bus. So the bus number is also very good.

The device number of a pci bus is determined by the connection relationship between the idsel signal of the PCI device and the pci bus address line, that is, the bus number and device number of each PCI slot are fixed. This is determined by hardware engineers. Ask them.
The PCI function number is related to the specific design of the PCI device. There are up to eight functional devices in a PCI device, and each functional device has its own PCI configuration space, while the vast majority of PCI devices have only one functional device. The host master Bridge uses the Register number to access a register in the configuration space of the PCI device.

In the host Main Bridge of the mpc83xx processor, registers related to the PCI device configuration space are composed of the pai_addr, pai_data, and int_ack registers. The system software uses the pai_addr and pai_data registers to access the configuration space of the PCI device, and uses the int_ack register to access the interrupt vector of the interrupt controller mounted on the PCI bus.

The mpc83xx processor uses the cfg_addr register and the cfg_data register to access the configuration space of the PCI device. The cfg_addr register is used to store the ID number of the PCI device. The fields of this register are described as follows:

Enable bit: When this bit is 1, the host main bridge can access the configuration space of the PCI device. When the host processor accesses the cfg_data register, the host master bridge converts access to this register into PCI read/write bus transactions and sends them to the PCI bus.

Bus number field: record the bus number of the PCI device.

Device number field: record the device Number of the PCI device.

Function number field: record the function number of the PCI device.

Register number field: record the configuration register number of the PCI device.

For the mpc83xx series Processors, when accessing the configuration space of the PCI device, you must first set the bus number, device number, function number, and register number corresponding to the PCI device in the pai_addr register, then enable the bit. Then, when the processor reads and writes the cfg_data register, the host master bridge converts the read/write access to the memory into a PCI configuration read/write request and sends it to the PCI bus. If the Enable bit is not enabled, the processor's access to ipv_data is only a common I/O access, and the host master bridge cannot convert it into PCI configuration read/write requests.

Note: In the PowerPC processor, the data stored in the cfg_data register adopts the big-end mode, while the PCI configuration register of the PCI device adopts the small-end alignment. So pay attention to byte sequence conversion.

When the powercp processor reads int_ack, the host converts the read operation into a PCI bus to interrupt the response transaction.

It is the configuration space of 64 bytes that the PCI device must support. The value range is 0x00-0x3f:

 

Many PCI devices only support 64-byte configuration space. The differences between PCI and PCIe configuration spaces are as follows:

PCI/PCI-X and PCIe devices also extend the 0x40 and 0xff configuration space, which primarily stores capability structures related to MSI or MSI-X interrupt mechanisms. All PCIe devices that can submit interrupt requests must support the capability structure related to the MSI or MSI-X interrupt mechanism.

The PCIe device also supports the 0x100-0xfff extension configuration space. The maximum extended configuration space of a PCIe device is 4 kb. The extended configuration space of the PCIe bus stores some of the Capability structures unique to the PCIe device. The PCI device cannot use this space.

In the x86 processor, the config_address and config_data registers are used to access 0x00-0xff, while the ECAM method is used to access the space of 0x000-0xfff. In the PowerPC processor, the pai_data and pai_addr registers can be used to access 0x000-0x.

PCI-X and PCIe bus specifications require that their devices support the capabilities structure. There is a capabilities pointer register in the basic PCI configuration space, which stores the header pointer pointing to the capabilities Structure linked list. A PCIe device can contain multiple capability structures, including power management, PCIe bus-related structures, interrupt request-related structures, PCIe capability structures, and PCIe extended capability structures.