Creation Time and Retention Time

Overview Understanding: 1. Setup Time: the time when the data remains unchanged before the rising edge of the trigger's clock signal. If the setup time is not enough, data cannot be pushed into the trigger at the rising edge of the clock. That is, before the time (Setup Time) trigger arrives, the data at the input end of the data must remain unchanged; the Creation Time determines the maximum latency of the combination logic between the triggers.

2. hold time: it refers to the time when the trigger's clock signal rises and the data remains unchanged. If the holding time is not enough, the data cannot be pushed into the trigger; another understanding is that after the arrival of the clock, the data at the input end of the hold time trigger must remain unchanged; the retention time determines the minimum latency of the combined logic between the triggers.

3. Setup Time and hold time,1:

 

 

4. In addition, stable data transmission must meet the requirements for establishing and maintaining time. Of courseIn some cases,Creation Time and Retention TimeThe value can be zero. PLD/FPGA development softwareThe creation and retention time of two related inputs can be automatically calculated.   

Considerations for establishing the time retention period

Huawei title: The clock period is t, and the trigger D1 can be created at most T1max and at least T1min. The maximum latency of a combined logical circuit is T2max and the minimum is T2min. Q: What are the conditions for the creation time t3 and retention time t4 of trigger D2?

Analysis:

Tffpd: the response time of the trigger output, that is, the time for the trigger output to change and be stable after the CLK clock rising edge. It can also be understood as the trigger output delay.
Tcomb: the time required for the trigger output to pass through the combination logic, that is, the combination logic delay in the question.
Tsetup: Creation Time
Thold: Retention Time
Tclk: clock period
Build time margin: This is equivalent to the Protection time, where the time margin must be greater than or equal to 0.
Persistence Duration: The persistence duration must be greater than or equal to 0.

It can be seen that the established time margin = tclk-tffpd (max)-tcomb (max)-tsetup, based on the established time margin ≥ 0, that is, tclk-tffpd (max) -tcomb (max)-tsetup ≥0, you can get the trigger D2 tsetup ≤tclk-tffpd (max)-tcomb (max), because tffpd is not considered in the question, so we think tffpd = 0, so we get tsetup ≤ T-T2max.

It can be seen that the persistence time margin + thold = tffpd (min) + tcomb (min), so the persistence time margin = tffpd (min) + tcomb (min)-thold, based on the persistence time margin ≥ 0, that is, tffpd (min) + tcomb (min)-thold ≥ 0, you can obtain the trigger D2 thold ≤ tffpd (min) + tcomb (min ), because tffpd is not considered in the question, we think that tffpd = 0, so we get thold ≤ T2min.

 

When the input signal of the trigger D2 is still at the holding time, if the output of the trigger D1 has reached the input of the D2 through the combination logic, this will damage the data that D2 should have kept.