Cyclone II 2-port Ram Compile Error resolution method

The following error occurred at compile time after recently using 2-port RAM in the Quartus II 9.0sp2 Web Edition selection ep2c5q208c8n chip compilation project:

ERROR:M4K memory block WYSIWYG primitive "Vram8k:vram8k_inst|altsyncram:altsyncram_componen t|altsyncram_3s62:auto_ Generated|ram_block1a0 "utilizes the Dual-port dual-clock mode. However, this mode isn't supported in Cyclone II device family in this version fo Quartus

Workaround:

1.

Open the project settings and navigate to the ASSIGNMENTS on the left side of the tab | SETTING | Analysis&synhesis "page;
Then add a parameter with the name (name) Cycloneii_safe_write, the value (default SETTING) to Verified_safe in the default parameter setting (Settings_default patameters);
Then click "ADD" and press "OK" to confirm.

So modified after compiling, although the error is not, but has become warning, do not know whether it will affect the project.

2, or the 1th method, just to change the verified_safe into a restructure, and then compile, warning, hope to be able to use normal.

Copyright NOTICE: This article for Bo Master original article, without Bo Master permission not reproduced.

Cyclone II 2-port Ram Compile Error resolution method