Cyclone III prototype development and debugging

Reprinted: http://blog.ednchina.com/ilove314/1819329/Message.aspx

The recently designed cyclone III prototype board is the first device that allows privileged users to access cyclone III. Some problems have been encountered in the schematic diagram, PCB drawing, and pin distribution. These problems are more or less caused by the carelessness of the individual who is not familiar with the new device and the design. It mainly targets the board-level hardware design. Here we will make a messy list and make a summary. We will learn more in the future and avoid low-level mistakes as much as possible.

1. first, an unsolved problem should be raised. ep3c5e144/ep3c10e144/ep3c16e144/ep3c25e144 is a device with full compatibility with various resources on the pins. Altera is very commendable in this regard) unavailability exists in the piin11 and pin12 of the device, this problem occurs when an Apsara stack controller is integrated into a nios2 system and Cyclone II does not need to allocate pins of This EPC controller (internal automatic ing), cyclone III requires manual allocation (you need to move the script to setting in advance). The dclk of the Apsara stack management framework must be allocated to pin12. A D0 foot of the SDRAM is allocated to pin11 in the project. An error occurred when compiling to fitting . I found no effect in handbook. I turned to the search engine and finally found that someone encountered the same problem, but the solution was not: pin11 or pin12. The privileged student is helpless on this issue. It is estimated that the two legs of the cyclone III device have made some checks such as signal coupling , and you do not know whether to perform some settings in the tool options to cancel such checks. We are also looking forward to hearing from friends who have encountered the same problem and telling the privilege how to solve the problem.

2. Let's talk about two very low-level mistakes, which are silly and have no technical skills. We can only give ourselves a warning: we must be clear-headed when working. The two errors are related to the BOM and network labels respectively. This error is due to two three-end voltage regulators-1.2 and-2.5 On the schematic diagram. Because the pin definition and encapsulation are the same, I did not pay attention to it, fortunately, only the BOM table labels are affected at the end, but this also led to the terrible change of the switch positions of 1.2v and 2.5v during the first model welding. The result can be imagined that ep3c10e144c7 was suspended, very distressed. Another mistake is a bit ridiculous. privileged students are generally used to adding LED lights to idle ports. The first thing for FPGA initial debugging is to let him flash up, during work hours, LEDs are also used to flashing as instructions for running the work. When drawing the schematic diagram, I copied a previous drawing directly without paying attention to the network label. As a result, the Gnd of the LED is not connected to the general dgnd of the system, at the end of the debugging, the output current of cyclone III was suspected to be too small, so that a single lamp would strike.

3. Several cyclone III voltages are also different from those of the previous series. vccios are not mentioned and designed based on user requirements;Vccint is 1.2 V, Is the same as Cyclone II. Pay special attention to the power supply of the PLL, that is, vcca and vccd, and vccd provide the same pressure as the core for 1.2v, vcca usually requires some recommended decoupling circuits, which are not 1.2 V,2.5 V is requiredThe privileged student also made a mistake here. Fortunately, both vcca power portals passed through the magnetic beads, so it was a temporary emergency to fly two lines in time after finding the problem. The voltage of the JTAG circuit is also different from that of the past. Here is a discussion of the following.

4. Cyclone III standardsThe recommended JTAG interface voltage is 2.5 V.Of course, it seems that you can download it when 3.3v is used, but you still work according to the officially recommended voltage to avoid unnecessary troubles.

5. also, some circuit debugging sequence of the prototype design may not only need to be done in the prototype design, most of the time, the first board we need to re-build the system to debug with something we are familiar with also needs to have a debugging order. In short, generally starting from the power supply, we must first ensure that the voltage of each file is normal. Secondly, we need to weld the crystal oscillator and reset circuit, FPGA and download circuit, and then perform board-level verification, ensure that the configuration circuit and Device of FPGA work normally, and finally weld other peripheral circuits.

6.There is a large grounding pad at the bottom of the cyclone III device, Square. The privileged employee did not pay attention to the canvas and directly called the encapsulation in the alicloud designer library. I get a little worried about the board, because usually used to make the board when the hole is covered with oil buried, so as to avoid some unexpected metal falling board connecting through the hole as a short circuit, the bottom of the cyclone III device package has a lot of holes, but it becomes impossible to heat the bottom of the pad, nor can it ensure that the Gnd at the bottom of the device is effectively connected. In the end, I had to make the best decisions. I took a drilling tool and made a hole. After welding, I had some tin to ensure that the ground was connected. Therefore, we should considerLarger HolesTo ensure the solderability.

7. learn to use a wide range of development documents, such as the first time you get started with Cyclone III, Altera's official "An 466: Cyclone III Design Guidelines" is a very good reference document, chinese versions translated on the Internet are also flying. Privileged students will find this article only when there is a problem later.ArticleThe application note has been lying on its own hard disk and has not been turned over. You should read this application note early.

8. the default PLL phase compensation is C0. In other series devices, C0 is generally not used to output the clock of the external pin, while the C0 is the only PLL output that can be directly output to the external pin for clock . Privileged students found in practice that this C0 cannot be used as phase compensation. If the default C0 is used as the compensation pin, besides Quartus II will give a warning, what's even more terrible is that it may cause some time series troubles to the clock-controlled chip output by C0 in the system. Use another PLL to output the internal driving clock as the phase compensation. The specific reason is not clear to the privileged personnel. Later I hope to study the mechanism of PLL phase compensation, and I will write an article to discuss my understanding.