DBAu1200 Development Board Boot Flash Address

// ================================================ ========================================
// TITLE:
// DBAu1200 Development Board Boot Flash Address
// AUTHOR:
// Norains
// DATE:
// Wednesday 16-10000l-2008
// Environment:
// PB 5.0 + DB1200 BSP
// ================================================ ========================================
I have read my friend "discussing the Boot Flash of DBAU1200 Development Board" and may be confused about the BOOT FLASH Address. The boot flash Address (including parameter flash) is 0x1C000000 ~ 0x1FFFFFFF, how is this address defined?

You can find this address in "$ Platform/Db1200/Inc/db0000.h:

// FLASH on RCE0
//
# Define flash_base 0x1c000000
# Define flash_size 0x04000000
# Define boot_vector_offset 0x1fc00000-flash_base

The base address is 0x1c000000, and the flash size is 0x04000000. The sum of the two is equal to 0x1fffffff, which is exactly the top address of flash.

Although we know that the definition is in this file, we still do not know why this address is defined. Therefore, we need to check the Au1200 documentation and find that there is a list of physical addresses () as follows ():

We can clearly see that 0x0 18000000 ~ 0x0 1fffffff is the address defined specifically for the boot Rom. The explanation clearly states that the boot Rom address must contain the boot vector, that is, 0x1fc00000. Therefore, for dbau1200 Development Board, the base address must be identified using the following method: 0x1fffffff-0x04000000 + 1 = 0x1c000000. Because it starts with 0, we need to add another 1.

The address value of dbau1200 Development Board boot flash is clear, and now another question comes: Check the list carefully and you will find that the address ranges from 0 to 0 20000000 ~ 0x0 7fffffff segment can also be used as memory mapped. Why do we need to associate it with 0x0 18000000 ~ 0x0 1fffffff is separated? In fact, the problem is very simple, but it involves the MIPs processor mechanism. We know that the physical address range mapped between the MIPs processor kseg0 and kseg1 is 512 m, and the base number of this range is exactly: 0x00000000 ~ 0x0 1 fffffff, which falls within the boot flash range described in this document. In other words, the physical addresses accessible through kseg0 and kseg1 are only 0x00000000 ~ 0x0 1fffffff range, the rest can only be through the MMU mechanism. Careful friends may have guessed that if our boot flash is larger than 128 MB, for example, 1 GB, we can only access the first 128 MB through kseg0 or kseg1, the remaining capacity is unmeasurable. This is why the document divides the space that can be used for memory mapped into two segments.