DDR2 Design of cyclone IV

Nowadays, in FPGA system design, the complexity of the system is getting higher and higher, and the requirements for memory are getting higher and higher. Generally, DDR2 has become the first choice for FPGA systems considering the overall volume and capacity. Here, we will make a summary of the DDR2 design for the cyclone IV series FPGA. The FPGA and DDR Design for other series are similar.

According to the cyclone IV manual, FPGA pin allocation should be considered during DDR2 design, rather than randomly allocated.

 

First, describe the DDR2 signal pins. Here we useMt47h128m8(16meg × 8bit × 8banks.

Its signal line (34 in total) includes:

Clock and control line: CLK + /-, Cke, Rasn, Casn, CSN, Wen;

Data Control Line: ba0 ~ Ba2, Dqs, Dqm;

Address line: a0 ~ A13;

Data Cable: D0 ~ D7;

 

In FPGA, in order to better utilize the performance of DDR, it will impose related constraints on the distribution of DDR pins.

Here we useEp4ce75f23c8nFor example, f484 encapsulation.

It is in progress8Bit DDR2The relatedDQDqsAnd dqmPin. We should follow these pin constraints during design.

These pins are specified on the top, bottom, left, and right of the FPGA:

Each direction is divided into four zones. If you select an 8-bit DDR, each zone has nine DQ pins and the corresponding dqs, dqm:

(1) left:Dq0l, Dq1l, Dq2l, Dq3lAnd dqslAnd DML;

(2) below:Dq2b, Dq3b, Dq4b, Dq5bAnd dqsbAnd DMB;

(3) Right:Dq0r, Dq1r, Dq2r, Dq3rAnd dqsrAnd DMR;

(4) above:Dq2t, Dq3t, Dq4t, Dq5tAnd dqstAnd DMT;

 

For exampleDq5b, The nine DQ pins are: Y10, W10, V11, aa8, aa9, ab8, U10, Y8, ab7, and ab9 (dqs), aa7 (dqm ).

 

Therefore, during hardware design, the corresponding pins (eight-Bit Data DQ, dqs, dqm) should be correctly allocated, as for the location of the Eight-bit DQ data, you can adjust the locations based on the convenience of wiring,Ensure they are in the same zoneOther DDR2 pins (address line, control line, etc.) can be allocated randomly according to the convenience of wiring, but mustAllDDR2All the pins in FPGAThe same or two banksZone(For example, bank3 and bank4, because sometimes one bank zone cannot hold all these pins ).To facilitate the unification of themVccioSpecify the voltage and consider the future PCBEase of wiring, Note thatBankVccioThe voltage must be 1.8 V.

In Quartus II, proper pin allocation is also required, and pay attention to theseThe level standard is 1.8 V..

If the related pin distribution is not performed according to these constraints during hardware design, an error may be reported during Quartus II Compilation, resulting in DDR2 malfunction.

 

I would like to share with you my personal experience in design.