Depressing asp! Depressing PV!

Depressing asp! Depressing PV!

The reason is that sometimes the MCU + FPGA/CPLD joint debugging is not enough for me to use epm240t100c5n, instead of drawing a larger resource CPLD, I chose ep2c5t144c8n, which is the most cost-effective FPGA.

I drew a board, invested in Shenzhen, waited for the Board and other components, and finally got everything ready one day. I had nothing to worry about, so yesterday I calmed down and shouted a board. It was pretty Haha, but I was scared, i'm afraid I won't be able to do it because I drew c ii for the first time and I used to draw CIII (haha). Fortunately, except for a small problem, the JTAG will be ready soon, but what I'm depressed about is, why can't I do this? I'm depressed. I inserted the ASP port, checked the circuit, magnifier, air blow gun, multimeter, and jumper. I still couldn't, but I had to go to bed.

Nnd gave up everything in the morning because of depressed mood and depressing asp! Depressing PV! No matter what it is, I plan to weld a piece in the calm down, and I will not be able to do it any more. I will test the Working Sequence of the nconfig, conf_done, nce, and data0 pins one by one with the oscilloscope, i'm crazy.

As a result, the reason for the character may be that we have re-welded a piece of it, or JTAG, but ASP still does not work. The first is that the javascript can be downloaded in ASP, but cannot be reloaded, it seems that data cannot be written into FPGA during configuration. I am depressed. I have read a lot of circuit diagrams and many development boards (many of them are wrong due to professional ethics, after reading a few books, I couldn't find out where I was wrong. I was depressed.

In the afternoon, I tried to use JTAG to download the Apsara stack management framework. The result is displayed, and the configuration is successfully reloaded. However, the two Boards are the same, and ASP is still unavailable. Although it is functional, it can be implemented in an abnormal way. Although it is now used by the PV, it is no longer used for fear of power loss, but I am still depressed. Below is my JTAG & ASP Circuit

I can't find anything, and it's not reliable. It's no different from the successful Board of others (the design of Altera FPGA/CPLD says data0.dclk is going to be pulled up, the purpose is to give a stable State after the configuration is complete, but there is no need in fact), I am quite depressed, depressed why ASP is not good, depressed why does it work ??

Just a few clicks on the Internet, some people are struggling with the same problem. asp can now be used, but cannot be reloaded and cannot be configured, but after converting it into a JIC file, you can use JTAG. The same tangle, the same depressing, is really speechless.

For an electronic project, it is very painful to find the problem. If you find the path to the problem, you don't know why the problem is more painful; however, I found out why such a problem exists, but I don't know how to solve the problems that are more painful. At this time, I found the problem, but I don't know why or how to solve it. I am so worried. I am crazy, but I am forced to calm down, this is really nothing to bear.

A hero cannot endure what others are willing to endure!

It's really speechless. If anyone has a common language, I hope I can help me with FPGA. Sometimes, I still have to be able to withstand the attacks! We have been growing since the cycle of fight and recovery.

Depressing ASP, depressing PVS !!!