Design a simple processor (5)-SEQ + CPU implementation

The ultimate goal is to design a CPU with a sequential nature.
The CPU reschedules the computing phase, moves PC computing to the fetch phase, and obtains SEQ +
CPU.

 

 

SEQ +:Reschedule the computing phase

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Re-adjust the activity of the update PC phase at the beginning of a clock cycle so that it can calculate the PC value of the current command. This is the difference between SEQ and SEQ + PC computing.

 

In SEQ +, to calculate the current PC, you need to use registers to save the signals generated in the previous cycle, as shown in:
PlCode, pCnd, pValM, pv1c, pvalkaline.

We found that the program register PC does not use the hardware register, but uses the control logic to dynamically calculate the PC. it indicates that a processor can be implemented in a different way than the conceptual model implied by ISA.

 

 

SEQ +Hardware structure

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Note *: the pictures in this article are from the book's official website, I made a transformation (comment and add), see the http://csapp.cs.cmu.edu/public/figures.html

(Copyright 2011, Randal E. Bryant and David R. O 'allaron)

 

Reference:

1. in-depth understanding of computer systems (formerly known as 2nd)

 

(Copyright, reprinted with the author and source-dennis_fan-http: // blog.csdn.net/dennis_fan
)