Farewell to ASP (active serial programming) download Mode

Farewell to ASP (active serial programming) download mode-JTAG---EPCS1 order

For a long time, most people download FPGA Configuration chips in ASP download mode. It is really troublesome to plug in the USB blaster interface. In fact, downloading FPGA Configuration chips, another method is to download the JIC file or the jam file through the JTAG and another configuration mode. For actual development, it is of little significance to general experiments, but for batch development, not only can the cost of the Board be reduced (because the ASP download interface is not used, and the area is reduced), but also a lot of devices are saved and should be cost-effective.

The specific practices are described in detail below to make development easier.

Farewell to ASP (active serial programming) download mode... 1

JTAG---EPCS1. 1

Order... 1

I. Comparison of child Apsara stack in ASP and JTAG modes... 2

Flowchart... 2

Serial flash loader 2

2. configuration download process... 3

1. Create a project... 3

2. Compile water_led.v. 3.

3. IP address added to serial flash loader 4

4. Add a program... 4

5. Convert the sof file to a JIC file... 4

6. convert a JIC file to a jam file or an SVF file... 7

7. program the serial configuration device and download the program... 7

9. effect... 7

3. Feelings of conclusion... 7

I. Comparison flowchart of child Apsara stack in ASP and JTAG Modes

Serial flash Loader

The serial flash loader, SFL, provides the ability to program an active serial configuration device through the FPGA's JTAG pins. the SFL creates a bridge between the fpga jtag pins and the fpga asmi interface. the SFL, which consumes ~ 188 logic elements, must be encoded in the design as this instantiates the bridge. The SFL bridge is instantiated using the Quartus II megawizard plug-in manager.

2. Configure the entire process of download 1. Create a project 2. Compile water_led.v

Module jtag_epcs1 (

Input CLK, // 50 MHz on the board

Output Reg [7:0] water_led

);

Reg [21:0] CNT;

Reg clk_led; // 10Hz

Always @ (posedge CLK)

Begin

If (CNT <22 'd2500000)

CNT <= CNT + 1' B1;

Else

Begin

CNT <= 0;

Clk_led <= ~ Clk_led;

End

End

Always @ (posedge clk_led)

Begin

Case (water_led)

8 'b00000000: water_led <= 8' b00000001;

8 'b00000001: water_led <= 8' b00000011;

8 'b00000011: water_led <= 8' b00000111;

8 'b00000111: water_led <= 8' b00001111;

8 'b00001111: water_led <= 8' b00011111;

8 'b00011111: water_led <= 8' b00111111;

8 'b00111111: water_led <= 8' b01111111;

8 'b01111111: water_led <= 8' b1111111111;

8 'b11111111: water_led <= 8' b1111111110;

8 'b11111110: water_led <= 8' b11111100;

8 'b11111100: water_led <= 8' b11111000;

8 'b11111000: water_led <= 8' b11110000;

8 'b11110000: water_led <= 8' b11100000;

8 'b11100000: water_led <= 8' b11000000;

8 'b11000000: water_led <= 8' b0000000;

8 'b0000000: water_led <= 8' b00000000;

Endcase

End

Endmodule

3. IP address added to serial flash Loader

4. Add Program

Serial_flash_loader u_s (

. Noein (1' B0)

);

Endmodule

5. Convert sof files to JIC files

(1)

(2)

Select JTAG indirect configuration file, epcs1, And the saved JIC file name.

Select Memory Map File

(3)

Select target board Device

(4)

Add a sof file to the project in SOF data to convert it to an MIF file.

(5)

Select the mode for compressing sof files to Reduce Space

Conversion successful

6. convert a JIC file to a jam file or an SVF file.

Alternatively, this one is optional. I don't know what it means to download 7th programs directly. If you are interested, refer to the Configuring EPC devices via JTAG V1.0 document.

7. Programming serial configuration devices and downloading programs

9. Effect

After the program is restarted, the flow lamp starts to flow, indicating that the program has been downloaded to the PV chip through JTAG to implement the desired function.

Iii. Conclusion feelings

When I first got started with this item, I used q II version 9.1. I tested a lot and read a lot of PDF files, but I just couldn't download it, at that time, I thought it was the reason for the Board and sub-circuit, or the preparation method was wrong, so I had no time to do it. At that time, I had never touched anything else.

Later, I remember that at the end of last year, a netizen told me that Q II 9.1 had a bug and there was a problem with the curing program, still, the JTAG download mode cannot be used to download the configuration to the Apsara stack. Later, fans directly asked Altera for help. Finally, soon, q ii 9.1 SP1 was released, probably a patch, it's not very small or very big to cover the installation. Now, it's okay. It's not my fault for so long. It's a software error.

Now good, huh, tell you my experience, also hope not to walk like me, still using q ii 9.1 friends, or hurry to ftp://ftp.altera.com/outgoing/release/ download q ii 9.1 SP1, it's a waste of time.