FPGA design's tips

1. Do not write too many state machines. Instead, use small state machines to associate with each other.

 

2. We recommend that you use timequest for time series constraints. The advantage is that it may compare your time series constraints with your design. Before doing time series analysis, first, analyze your constraints, and then tell you how many things you have to do that you have not done (for the restricted path, not implemented (ignored timing requirements ).

 

3. The clock constraints should focus on two phenomena. First, introduce the logic in the clock path as little as possible. Otherwise, the skew between the clock and the clock may occur. In addition, the clock is used to collect data for both the upstream and downstream edges. Pay attention to the clock constraints. Otherwise, your circuit will not know where to fly.

 

4. One of the most important constraints is to avoid them. There are many disadvantages of over-constraints, such as increasing Compilation Time and excessive resource usage, leading to other timing problems. If you are not at ease with your own constraints, or there may be slight differences between the device and the device, you can make some margin for the constraints, but it is absolutely undesirable to pass over the constraints.

 

5. IP is used to complete a specific function, so we do not need to know how it is implemented. As an IP address, the most important thing is actually an interface, because you need to know how to make it work, rather than how it works. Therefore, when reading the document, we mainly look at the interface signal and have an understanding of the functions of all signals. For example, as a relatively large module, the Niosi CPU uses the aveon mm point-to-point interface. What is different from the common PCI interface is that it supports multi-line control at the same time. Because it does not have the concept of bus, it will not be able to communicate with any other communication when the bus is occupied. Niosii is directly used in the system builder. We do not need to know the specific signal, because it is not necessary, and we cannot see these interfaces. In nioⅱ, we have two master aveon mm interfaces, one is the instruction master port, which is the interface for the CPU to read commands. The CPU uses this port to read commands from memory. The other is the data master port, which is used to connect to the data channel. For example, the data you want to read and the data you want to store all follows this channel. These two ports can be connected to the same memory. In this case, you need to be very careful. It is very likely that you have replaced your own commands. But what can we do in turn? Software can be changed based on the situationCode. There is also the third port in nioⅱ, which is used for debugging. There are other interfaces, such as the TCM interface. We need to know the existence of these interfaces, but do not need to know the details. We only need to go to the relevant documents when using them.

 

6. As a system design, there is a need for a coarse-grained model, without wasting time on details. You will find that many details are meaningless. It doesn't mean that we don't need to study details. Details are very important, but they only need to be followed when they are used.

 

7. Unexpected pain points may occur when IP addresses are used. Therefore, do not use assumptions to imagine the Module Settings. Instead, try to adapt to the environment and configure your own design. As an FPGA player, this ability to change according to the environment is required.

 

8. Considering cashes settings, there are two types of cash: one is used for instruction caching and the other is used for data caching. Cash size pairProgramThe running speed of is affected. Of course, there is no need to use too many resources. Enough.

 

9. Set custom commands. This is the most valuable setting. Custom commands are not software macros or functions. But a piece of hardware. When the CPU calls this command, it actually calls this hardware module, which is embedded in the CPU. This is actually a fun place for niosiii.

 

10. The system is built, developed, and maintained on the system platform in quartuⅱ. Although we often use it as the development environment of an embedded system of niosii, I don't want to limit my thinking to niosii. It will become a platform that embraces all system content.

 

11. There are two types of aveon-mm interfaces, one is aveon-mm interface and the other is aveon-ST interface. The mm interface is used to read and write data through the address, and more is used in the control logic. The St interface is a point-to-point stream data interface, and more can be used in the middle of a module with a high-speed pass rate. There is no conflict between the two interfaces. It is not to say that there are no conflict between them. A module can have both the MM interface and several mm interfaces, or the st interface at the same time. As a point-to-point interface definition, aveon can achieve efficient interface effects. This is essentially different from bus interfaces such as PCI. The PCI bus can be regarded as a railway track. When a train is traveling on a railway track, it cannot be used by another train at the same time. The aveon interface is more like a highway, and vehicles can travel in two directions.

 

12. As a unique principle in FPGA design, the world is not created by you, so you must adapt to it, rather than be stubborn.

 

13In FPGA, except that the delay between the gate and the door is fixed (clock frequency), the delay of all the combined circuits is uncertain. Remember this rule. Any signal that has not been shut down by the door is unstable and only temporary.

 

14. Before we generate a new regeneration gate (some logic results drive a gate as a clock, and we call it a regeneration gate, you 'd better close the clock signal with the original door. In this way, you will get a clean, pure clock signal.

 

15. For new devices, the device itself can provide some clock control modules. When you need to use gated lock, try to use these modules, it will make your clock secure (clock control block ).

 

16. If you have to use a logical circuit to lock the door, your device does not have a specific module. In this case, you can first use the clock to turn off your lock signal. The advantage is that the glitch signal can be completely avoided outside the door, making your clock safer.

 

17. Initial power-on value
in general, the output of all doors is low when power is on. However, this cannot be changed. You can set power-on to high, so that the integrated tool may do two things, reverse the output, or use Preset Control (if any) to put the initial value into the door.
the high power-on method was not necessary, because you can actually use the reset signal to obtain the initial state you want. if you think this is necessary, you can do the following: