GNU make learning Summary

 

 

I wrote a simple general makefile template to compile CPP or CProgramSee the next log.

Http://blog.csdn.net/felixit0120/article/details/7663756

 

GNU make learning summary:

1. $ (patsubst pattern, replacement, text)
Function: search for words separated by spaces in "text" and replace pattern with replacement. The pattern wildcard % can be used in the pattern parameter to represent several characters in a word. If the replacement parameter also contains a %,

In replacement, % is the character represented by % in pattern.
Example: $ (patsubst %. C, %. O, X. c. c bar. c)
Returns the string "x. c. c bar. C ". the word ending with C is replaced. o. The return result of the function is "x. c. O Bar. o"

2. Simplified patsubst
$ (VaR: pattern = replacement) equivalent $ (patsubst pattern, replacement, $ (VAR ))
In addition, it is easier to replace the character Suffix:
$ (VaR: suffix = replacement) equivalent $ (patsubst % suffix, % replacement, $ (VAR ))
For example, we have a variable that represents all. O files. It is defined as "objects = Foo. O Bar. O Baz. O ". To obtain the. C source files corresponding to these. O files. We can use either of the following two methods:
$ (Objects:. O =. c)
$ (Patsubst %. O, %. C, $ (objects ))

3. $ (wildcard pattern)
Function: Lists All file names in pattern format in the current directory.
Function Description: "pattern" uses shell-recognizable wildcards, including? (Single character), * (Multi-character), etc.
Example: $ (wildcard *. c)
The returned value is the list of all. C source files in the current directory.
Complex usage: You can use $ (patsubst %. C, %. O, $ (wildcard *. c ))
First, use the wildcard function to obtain. c file list, and then replace the suffix of all file names in the list. o. o file list.
In a directory, you can use makefile of the following content to compile all. c files in the working directory and connect them to an executable file.

Objects: = $ (patsubst %. C, %. O, $ (wildcard *. c ))

Foo: $ (objects)
CC-O Foo $ (objects)
Here, the implicit rules of make are used to compile the. C source file.

 

4. General Search (variable vpath)
Make can identify a special variable vpath. you can use the variable vpath to specify the search path of the dependent file. When the dependent file of the rule does not exist in the current directory, make searches for these dependent files in the directory specified by the variable. this variable is generally used to describe the search path of the dependent files in the rule. In fact, the vpath variable specifies the search path for all files in makefile, including dependent files and target files.
In the definition of the variable vpath, multiple directories are separated by spaces or colons. Make searches for directories in sequence install the sequence defined in the variable vpath (the current directory is always the first search directory ).
Vpath = SRC: ../Headers
The path specified by the vpaht variable is valid for all files in makefile. When you need to specify different search directories for different types of files, you need to use another method.

5. Selective search (keyword vpath)
Another way to set the file search path is to use the make vpath keyword (all lowercase ). It is not a variable but a make keyword.
It can specify different search directories for different types of files (separated by file names. It can be used in three ways.
1. vpath pattern Directories
Specify the search directory directorys for pattern-compliant files. Separate multiple directories with spaces or colons
2. vpath Pattern
Clear the search path set for the pattern-compliant file.
3. vpath
Clear all the file search paths that have been set.
The pattern in the vpath usage method must contain the pattern character %. %, which indicates matching one or more characters. For example, %. h indicates all files ending with. h.
Vpath %. h ../Headers
It indicates the. h file in makefile. If it cannot be found in the current directory, go to the directory ../Headers
Note: The path specified here is only available in the MAKEFILE file. h file. the path of the header file contained in the source file cannot be specified. the header file contained in the C source file must be described using the GCC command)

 

 

Automated Variables
$ @ Indicates the target file name in the rule. In a multi-target Pattern Rule, it indicates the target file name that triggers the rule to be executed.
$ <The first dependency File Name of the rule. If it is an implicit rule, it indicates the first dependent file specified by the target.
$ ^ List of all dependent files of the rule, separated by spaces. If the target is a static library file name, it represents only the names of all database members (. O. A file can appear repeatedly in the target dependency. The variable $ ^ only records its reference once. That is to say, the variable $ ^ will remove repeated dependent files.

 

 

The ultimate goal of makefile:

The first goal of makefile is the ultimate goal of this makefile.

The so-called ultimate goal is to make the final reconstruction of a rule in makefile.
In order to complete the reconstruction of the ultimate goal, it may trigger the reconstruction process of its Dependencies or dependent files.
By default, the ultimate goal is to appear in the makefile. Divide the result by the first target in the first rule starting with "dot." (if the first rule has multiple targets ).
Therefore, the makefile is written as follows: the compilation rules of the first target describe the compilation process and rules of the entire project or program. If the first rule in the makefile has multiple targets, the default ultimate goal is the first of multiple goals.
When we execute make in the directory where makefile is located, the default ultimate goal will be rebuilt.