LINUX compiler and Debug __linux

Linux compiler and debug under the Linux compilation and debugging ... 1 1. gcc/g++ compiler ... 1 2. Makefile use ... 2 2.1. Basic Process processing ... 2 2.2. Special handling and pseudo target ... 3 2.3. variables, functions, and rules ... 5 3. Program debugging ... 8 3.1. GDB Common Commands ... 8 3.2. GDB Application Example ... 9 3.3. Assert Assertion Macro ... 12 3.4. Error-handling functions and process exit functions ... 13 3.5. System log ... - 1. gcc/g++ compiler For C files in the. c format, you can use GCC or g++ to compile C + + files for. CC,. cpp format, you should use g++ to compile common options two        c for compiling source files       -o indicates output target file        g generates debug information in the target file for GDB debugging         d < macro definition > pass macro definition in at compile time-wall option to turn on all types of syntax warnings to help us determine that the code is correct and to be as portable as possible.   For example, there are two files Main.cpp,func.cpp main.cpp content is: #include <stdio.h> #include <stdlib.h> int MyFunc (); int main () {#ifdef _DEBUG     printf ("DEBUG MyFunc is:%d/n", MyFunc ()); #else     printf ("N DEBUG MyFunc is:%d/n ", MyFunc ()); #endif}   func.cpp content is: int MyFunc () {    return 123;}        compiled and connected parties The formula is as follows: 1,  g++-C Func.cpp will compile the func.cpp and generate a binary target file with the same name with the extension. o func.o the same reason g++-C main.cpp will compile main.cpp and generate the same name with the extension. O's binary target file MAIN.O 2, g++-C func.cpp-o func.o function same as (1), but explicitly specified the output file name MAIN.O         & nbsp Same reason g++-C main.cpp–o MAIN.O compiles the main.cpp and outputs the target file MAIN.O   3,   (1), (2) based on l         g++ MAIN.O func.o l         g++-o a.out main.o FUNC.O nbsp;    g++-o a.out *.o will connect to the target file MAIN.O and FUNC.O the final executable file a.out for the first, if you do not explicitly specify an executable file name, g++ defaults to A.out  & nbsp;     4,   the process of compiling and linking can also be combined into one process: g++ *.cpp g++ func.cpp main.cpp g++-o a.out func.cpp The specified source file will be compiled first, if successful, and then linked to an executable file a.out in the 4th way, in which a source file must have a main function, otherwise the chain is not connected.   5,   If you want to pass in a macro definition at compile time, use the-d parameter, such as g++-D _DEBUG *.cpp 2. Makefile Use 2.1. Basic Process Processing Makefile's working process is to organize the C + + source files that need to compile the connection into the file makefile, then run the Make program, the make program reads the makefile file information under the current folder, and according to the organization information in Makefile,               Call the corresponding Gcc/g++/shell program, complete the source file batch compilation and connection.               To write a makefile file, the home page must be clear about the concept of the target file and dependent file in makefile.               Typically, both the target file and the dependent file refer to the actual file. For example, there are makefile files with the following contents:

MAIN.EXE:MAIN.O func.o g++-o main.exe main.o func.o main.o:main.cpp g++-C main.cpp func.o:func.cpp g++-C func.cpp

                                           the file in the first line of the Main.exe is called the destination file, Two files     called Main.exe dependent files, separated by a space after the colon. It means that file Main.exe depends on file main.o and     func.o        the same reason:         Line 3rd MAIN.O is the target file, Main.cpp is main.o dependent file        The FUNC.O of line 5th is the target file, Func.cpp is the FUNC.O dependent file. The          file line 2nd (starting with the TAB key) represents the command to be executed for the target file to produce line 1th.   for the makefile file, the program make process is as follows:   1, the Make program first reads the target file in line 1th and its two dependent files main.o and FUNC.O; Then compare the generation time of file Main.exe and MAIN.O/FUNC.O if Main.exe is more than main.o/ FUNC.O the old word, execute the 2nd command to produce the target file Main.exe, otherwise make returns immediately, indicating that the target file does not have to rely on the file to be old and does not need to be updated. 2. Before executing the command in line 2nd, it first looks at other definitions in makefile to see if there are any dependent files for the target file in line 1th MAIN.O and FUNC.O, and if so, continue to match (1), (2). 3, according to (2) of the matching process, make program found that the 3rd line has the target file main.o dependent on main.cpp, then compare the MAIN.O with its dependent files main.cpp file new and old, if the MAIN.O than MAIn.cpp old, the command on line 4th is executed to produce the target file MAIN.O. When you execute the 4th command, Main.cpp no longer has a dependency file defined in the file makefile, the make program no longer continues to match, but executes the 4th command to produce the target file MAIN.O 4, The target file func.o is judged in the same way as above. Execution (3), (4) after MAIN.O and FUNC.O are generated, then the 2nd line of the command can be executed successfully, resulting in the 1th row of the target file Main.exe.   2.2. Special treatment and pseudo target First look at some makefile special case: Makefile file content is

A:echo ' a '

If file a exists during make, echo ' a ' will not be invoked to understand that file A is not dependent on the file, and that file A is always up to date, does not need to be executed, and if file A does not exist, echo ' a ' will be invoked.

A:b Echo ' a '

If file B does not exist, no matter if a is present, make will have an error if file B exists and file A does not exist, then echo ' A ' will be invoked if both files A and B are present, compare the file to the old in the normal way, deciding whether to invoke the Echo

A:b Echo ' a '

There are 2 sets of definitions in Makefile:

A:echo ' A ' B:echo ' B '

When make, if file A does not exist, echo ' a ' will be invoked, but Echo ' B ' will not be invoked, stating that the entry point of make execution is only one, the definition of the first target file, and other calls are invoked because of a direct or indirect dependency on the first definition; , which means that the specified entry point is B, then echo ' B ' is invoked, and Echo ' A ' is not invoked, and the entry point has only one

A:echo ' A ' b:a echo ' B '

When make B, the call order is echo ' a ' and then echo ' B ', indicating that the matching process of the dependent body is a full file match, not in the order down. Pseudo-target: Back to the first case in (2), if you want to specify an entry point of B, and call echo ' B ' regardless of whether file B exists, you can define B as a pseudo target:

A:echo ' a '. Phony:b B:echo ' B '

. Phony is the keyword of the makefile file, indicating that the target in the list after it is a pseudo target, so that Echo ' B ' will be invoked to execute make B, regardless of whether file B exists. Pseudo targets are often used in situations such as cleaning files, forcing recompilation, and so on, such as:

MAIN.EXE:MAIN.O func.o g++-o main.exe main.o func.o main.o:main.cpp g++-C main.cpp func.o:func.cpp g++-C FU Nc.cpp. Phony:rebuild clean Rebuild:clean main.exe clean:rm *.o *.exe

Performing make-clean clears the binary executable file in the folder and executes made rebuild the purge before recompiling the connection. 2.3. Variables, functions and rules As software projects become larger and more complex, the source files are more and more, if the previous way to write makefile files, will make makefile also become complex and difficult to maintain. By making the variables defined, used, built-in functions, and rules, you can write makefile files that are more versatile and make the same makefile file adaptable to the items you can't. Variable: Defines a name for a text string, which is the name of the variable, and the text string is the value of the variable. General methods for defining variables: Variable name = variable value recursive variable expansion (several variables share a value) or variable name: = variable Value simple variable expansion (similar to C + + Assignment) General method of using variables: $ (variable name) =??                ? Assign a value??? =$ (variable name) Reference example:

objs= main.o func.o main.exe:$ (OBJS) g++-o main.exe main.o func.o main.o:main.cpp g++-C main.cpp func.o:func.cpp g++-C Func.cpp

Make internally defines variables that are divided into two types, automatic variables and predefined variables: Automatic variables: When used, they are automatically replaced with specific values. Commonly used are:

Variable	Description
$@	Target file for current rule
$<	The first dependent file of the current rule
$^	All dependent files for the current rule, separated by commas
$?	A list of all related files in the rule that date is new to the destination file, separated by commas
$ (@D)	Directory name portion of the destination file
$ (@F)	File name portion of destination file

Predefined variable: It is also a previously defined variable within make, but its value is fixed and some values are empty. Commonly used are:

Variable	Description
$ (CC)	C compiler, default value: CC
$ (CPP)	c Preprocessor, default value: CPP
$ (RM)