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[Problem] pin planner usage problems: In Quartus I 7.2, Time Series Simulation However, the timing simulation changes once pin planner is used to set the pin, which is inconsistent with the functional simulation results and is not an ideal result. What should I pay attention to when using pin planner? [Answer] If timing simulation is performed when no pin is set, the subsequent simulation will be inaccurate. Because after the PIN is set, you need to re-wiring the layout, which is different from that without the pin, so the wiring change will naturally affect the timing change. The general practice is: first do all the settings, generate the network Table file and the delay file, plus the incentive file for simulation, the simulation results at this time is the closest to the actual situation. Generally, the pin setting has no specific requirements, and the difference signal is paired. So do not make a mistake. Use dedicated clock pins as much as possible for clock signals. There are no restrictions on common I/O, so you can do a good job of timing constraints.
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[Problem] how to configure the Cyclone FPGA pin function? [Answer] FPGA chip pins are divided into many categories, including general I/O, clock network, and reset network. The specific functions of these pins are selected during cabling. You can configure the features of these pins freely, but it is best to choose according to the chip Data Manual, such as configuring the clock to the dedicated clock pin, reset the configuration to the dedicated reset pin, otherwise, the final wiring result will be affected. 3. [problem] How to choose when assigning FPGA pins? What are the attributes of the pins that need to be considered? The pins in quartus2 have several attributes: reserved, group, I/O bank, vref group, what does I/O standard (3.3-V lvttl (default) mean? How can I set it? [Answer] I/O standard: This is used to support different level standards. The fpga I/O port voltage is introduced by VCC on the I/O bank. If 3.3 v ttl level is introduced to a bank, the entire bank outputs a v ttl level. Set this parameter to calculate power with current strength. The second is to load the correct pull-up/drop-down resistance on the IO port. As long as your settings are complete, Quartus will automatically route according to your level standards.
The second is Io Bank: Right-click Quartus pin planner's top view and Click Show Io banks. At this time, we will see that the FPGA pins are divided by several colors. Io ports in one color represent a group of banks. After the location constraint of the pin is completed. Io bank is automatically filled.
Third, Group: Group is the name of the signal you output. For example, you have a group of signals called CNT. You assign a value to one of CNT .. The Group is automatically filled with CNT.
Fourth, reserved: This restricts the I/O logic inside the pin. You can see some values below. Here are some introductions. Bidrectional: bidirectional, tri-state: three states, and so on. This constraint is the logic of the input and output regions of FPGA at the I/O end. For example, you choose tri-state. At this time, Quartus will automatically generate a three-state gate for you in the IO zone at the front of your IO port.
The fifth is vref group: this group is a subdivision of the bank, because a bank may have up to 60 feet. You can use this vref group to locate a pin quickly. (This is a non-modified attribute) cannot be modified. 4. [problem] My understanding: Io standard is set based on the level you want to enter, and the group is automatically determined based on the allocated signal port, the I/O bank of each pin is determined! In addition, is the IO bank of the allocated pins different? In addition to the difference between the dedicated pin and the user pin, what factors should be considered for Pin allocation? [Answer] understanding is correct. In addition, there is no problem with the signal spanning the IO bank. Only pay attention to whether the levels across banks are consistent. Latency across Io banks is not much latency for FPGA. Pin allocation. You can refer to the top view in pin planner in Quartus for the description of each pin. Most pins can be used as common Io. Only when there are some special requirements. Only corresponding Io can be used, such as differential input and high clock input. This is determined by referring to the I/O manual of the corresponding device. In addition, most device manufacturers provide reference designs. It includes IO Design, PCB design, and internal Program Port constraints. Therefore, the specific problem is analyzed. 5. [question] what is a pll )? What is the working principle of the Phase-Locked Loop? What are the requirements of the Phase-Locked Loop Circuit for hardware circuit connection?
[Answer] The Phase-Locked Loop is a feedback circuit used to synchronize the clock on the circuit with the phase of an external clock. The PLL synchronizes the phase of the external signal and the phase of the Controlled Crystal Oscillator (vcxo). During the comparison, the Phase-Locked Loop Circuit constantly adjusts the Clock Phase of the local Crystal Oscillator Based on the phase of the external signal until the two signals are synchronized.
In the data collection system, the phase-locked loop is a very useful synchronization technology, because through the phase-locked loop, different data collection boards can share the same sampling clock. Therefore, the phases of the local 80 MHz and 20 MHz time bases on all boards are synchronized, so that the sampling clock is also synchronized. Because the sampling clock of each Board is synchronized, data can be collected strictly at the same time.
the programming technology required to synchronize the sampling clock of multiple boards through the phase-locked loop varies depending on the hardware board you are using. For PCI bus-based products (M series data acquisition card, PCI digital devices, etc.), all synchronization is achieved through the clock and trigger line on the rtsi bus; at this time, one Board serves as the main card and outputs its internal clock. Through the rtsi line, other boards can obtain the clock signal for synchronization, the phase-locked loop is synchronized by synchronizing the clock of all boards on the 10 MHz backboard built in PXI. For more information about the Phase-Locked Loop Technology of different instruments, click the following link.
