SystemVerilog Grammar (10) __systemveri

21. Advanced Interface
A virtual interface (virtual interface) is a handle to a physical interface (handle).
The virtual interface and the corresponding common method can separate the design and verification platform to ensure that it is not affected by the design changes. When we make a change to the name of a design pin, we do not need to change the method of driving this interface, but only in the case of the physical transaction processor, the virtual interface to bind to the interface of the connected entity. In order to achieve greater reusability of the physical transaction processor.
Definition of Virtual interface: virtual interface_type name;
A virtual interface can be defined as a member of a class and can be initialized by building the parameters or procedures of a function.
Cases:
Interface Sbus;
Logic req,grant;
LOGIC[7:0] addr, data;
Endinterface

Class sbustransaction;
Virtual Sbus vif;
Function New (virtual Sbus s);
Vif=s;
Endfunction

Task request ();
    Vif.req <=1 ' B1;
Endatsk

Task Wait_for_bus ();
    @ (Posedge vif.grant);
Endtask

Endclass

22, SystemVerilog and C language interface
SystemVerilog introduces the direct programming Interface (DPI), which makes it easier to connect c,c++ or other non Verilog programming languages. Once you declare or import a C subroutine using the import statement, you can call it like a subroutine called SystemVerilog.
1. Example: SystemVerilog code calls C language subroutine factorial

C language factorial function

2. Parameter direction

4. Data type mappings between SystemVerilog and C languages

5, the use of C + + model test Platform

Using the C + + test platform

6. Export a SystemVerilog function