Requirements Description: IC design basics
Content: The difference between latches, triggers, registers, and buffers
From: The time of the poem
Original: http://www.cnblogs.com/wwping/articles/2261312.html
First, latch device
Latch (LATCH)---sensitive to pulse level, changing state under the action of the clock pulse level
Latches are level-triggered storage units where the action of the data store depends on the level value of the input clock (or enable) signal, and the output changes with the data input only when the latch is in the enabled state.
Unlike a trigger, which does not latch data, the output signal changes with the input signal, as if the signal passes through a buffer, and once the latch signal is latched, the data is locked and the input signal does not work. A latch is also known as a transparent latch, which means that the output is transparent to the input when it is not latched.
Latches (latch): The most I have heard is that it is level-triggered, hehe. Latches are level-triggered storage units, the action of the data store depends on the input clock (or enable) signal level value, when the latch is in the Enable state, the output will change with the data input. (Simply put, it has two inputs, respectively, is a valid signal en, an input data signal data_in, it has an output Q, it is the function of en effective when the data_in value to the Q, that is, the process of locking).
Application: The data is effective later than the clock signal. This means that the clock signal is first arrived, and the data signal is followed. Latches are sometimes used as data registers in some operator circuits.
Cons: Timing analysis is more difficult.
Do not latch for two reasons: 1, latch prone to produce burrs, 2, latches in the ASIC design should be said to be simpler than FF, but in the resources of the FPGA, most of the devices do not have a latch this thing, so need to use a logic gate and FF to form a latch, thus wasting resources.
Advantages: Small area. The latch is faster than FF, so it is appropriate to use the address latch, but it is important to ensure the quality of all latch signal sources, the latch is very common in CPU design, because its application makes the CPU speed much faster than the external IO component logic. Latch the door required to complete the same function is less than the trigger, so more in the ASIC.
Second, TriggerThe trigger (flip-flop, abbreviated as FF), also known as a bistable gate, is called a bistable trigger. is a digital logic circuit that can operate in two states. Triggers keep their state until they receive an input pulse, also known as a trigger. When an input pulse is received, the trigger output changes state according to the rule, and then maintains that state until another trigger is received.
Trigger (flip-flops) circuits are interconnected to form logic gates for digital integrated circuits (ICS) that use memory chips and microprocessors. They can be used to store a bit of data. The data can represent the status of the sequencer, the value of the counter, ASCII characters in computer memory, or any other information.
There are several different types of flip-flop (flip-flops) circuits with indicators such as t (toggle), S-R (set/reset) J-k (also known as Jack Kilby) and D (delay). Typical triggers include 0, one or two input signals, as well as clock signals and output signals. Some triggers also include an explicit input signal to reset the current output. The first electronic trigger was invented in 1919 by W.h.eccles and F.w.jordan.
The trigger (flip-flop)---sensitive to the pulse edge, and its state is changed only in the instant of the rising or falling edge of the clock pulse.
The T-Trigger (Toggle flip-flop,or Trigger flip-flop) has an input and output, when the clock frequency from 0 to 1 o'clock, if the T and Q are not the same, the output value will be 1. When the input T is 1, the status Q of the output is reversed, and the status Q at the output is unchanged at the time the input T is 0. The J and K input points of the JK trigger are connected together to form a T-trigger.
Application: The clock is effective later than the data. This means that the data signal is first established, and the clock signal is established. Enter the register at the time of the CP rising edge.
Three, registerRegister: A small storage area used to hold data for temporary storage of data and operation results for participating operations, which are widely used in various digital systems and computers. In fact, the register is a commonly used sequential logic circuit, but the timing logic circuit contains only the storage circuit. The memory circuit of a register is made up of a latch or trigger, because a latch or trigger can store a 1-bit binary number, so an n-bit register can be formed by n latches or triggers. The registers in the project are generally designed according to the number of bytes in the computer, so there are 8-bit registers, 16-bit registers and so on.
The trigger in the register only requires that they have the function of placing 1 and 0, so the registers can be composed either with the synchronous RS structure trigger or with the trigger of the master-slave structure or the edge trigger structure. Generally consists of D flip-flop, there is a public input/output enable control and clock, generally the Enable control terminal as a register circuit selection signal, the clock control end as a data input control signal.
Application of Registers
1. Can complete the data and string, string and conversion;
2. Can be used as a display data latch: Many devices need to display the value of the counter, in 8421BCD code count, seven segments of the display, if the number of high-speed, the human eye will not be able to identify the rapidly changing display characters. Adding a latch between the counter and the decoder, controlling the display time of the data is a common method.
3. Used as a buffer;
4. Composition counter: Shift register can be composed of shift-type counter, such as ring or twist ring counter.
Four, shift register
Shift register: Registers with shift function are called shift registers.
Registers are only functions that store data or code. Sometimes in order to process data, you need to register the data in the shift control signal, in turn to high or low to move 1 bits. Shift register according to the direction of the digital movement to move left, right, can control bidirectional (reversible) shift register, according to the data input, the output mode classification has serial and parallel points. In addition to the D-edge trigger forms a shift register, triggers such as JK can be used to form a shift register.
v. Bus Transceiver/Buffer
Buffer Register: Also known as buffer buffer: More used on the bus, improve the driving capacity, isolation before and after the stage, the buffer is mostly three-state output function. When the load does not have a non-selectable output as a high resistance characteristic, it will play a role in isolation, when the bus drive capacity is not enough to drive the load, will play a driving role. Since the buffer is connected to the data bus, it must have a tri-state output function.
It is divided into two types of input buffers and output buffers. The role of the former is to temporarily store the data sent by the peripheral, so that the processor can take it away, the latter is used to temporarily store the processor sent to peripheral data. With the numerical control buffer, the high-speed working CPU and the slow working peripheral can be coordinated and buffered to achieve the synchronization of data transmission.
Buffer: An area that transmits data between devices that are not synchronized at the initial speed or devices with different priority levels. Through buffers, you can reduce the number of waits between processes, so that when you read data from a slow device, the operating process of a fast device is uninterrupted.
The buffer is mainly called the computer domain. In the concrete implementation, the buffer is useful for the circuit of the latch structure, and it is also useful to implement the circuit without the lock structure. In general, when the two sides of the data to send and receive the work speed matching, the buffer can be used without the lock structure of the circuit to achieve, and when the sending and receiving data on both sides of the work speed mismatch, it is necessary to use a lock structure circuit to achieve (otherwise there will be data loss).
Buffers are used in many applications in digital systems:
(1) If the device with limited load capacity, you can add a buffer with a driver;
(2) The logic level between the front and rear levels is different, can be used to match the power-level converter;
(3) When the logic polarity is different or the univariate variable needs to be converted to a complementary variable, the inverse buffer is added, and (4) the buffer with Schmitt circuit is required to change the slow signal to the edge steep signal.
(5) data transmission and processing of different devices between the temperature and time, plus a buffer to compensate and so on.
Six, the difference between latch and trigger
Latches and flip-flops are memory-capable binary storage devices and are one of the basic components of various sequential logic circuits. The difference is: latch is related to all of its input signals, when the input signal changes latch change, no clock end, flip-flop is controlled by the clock, only when the clock is triggered to sample the current input, generating output. Of course, because both latch and flip-flop are timing logic, the output is related not only to the current input but also to the output of the same time.
1, latch by level trigger, non-synchronous control. The latch is equivalent to the path when the enable signal is valid, and latch remains in the output state when the enable signal is invalid. The DFF is triggered by the clock along with synchronous control.
2, latch is sensitive to input level, is affected by the delay of wiring, it is difficult to ensure the output is not burr; DFF is not easy to produce burrs.
3, if the use of gate circuit to build latch and DFF, then latch consumes less door resources than DFF, which is latch than DFF superior place. Therefore, the integration of latch in the ASIC is higher than that of DFF, but in the FPGA it is the opposite, because there is no standard latch unit in the FPGA, but there is a DFF unit, a latch need multiple le to achieve. The latch is a level trigger, which is equivalent to having an enable end, and is equivalent to a wire after activation (at the Enable level), which varies with the output. In the non-enabling state is to maintain the original signal, which can be seen and flip-flop differences, in fact, many times latch can not replace the FF.
4. Latch The static timing analysis becomes extremely complex.
5, currently latch only in the very high-end circuit, such as Intel's P4 and other CPUs. With the latch unit in the FPGA, the Register unit can be configured as a latch unit, and in the Xilinx v2p manual The unit is configured as a Register/latch unit, and the attachment is the Xilinx half-slice structure. Other models and manufacturers of FPGA are not verified. --personally believe that Xilinx can be directly matching and Altera may be more troublesome, to a few le, but also non-xilinx devices each slice can be configured this way, Altera only the DDR interface has a dedicated latch unit, In general, only high-speed circuits will use the latch design. Altera Le is no latch structure, and check the SP3 and sp2e, others do not check, the manual said support this configuration. For Altera's statement Wangdian said, Altera's FF cannot be configured as latch, which uses a lookup table to implement latch.
The general design rules are: avoid latch in most designs. It will let you design the timing of the end, and it is very covert, non-veteran can not find out. The biggest hazard of latch is the inability to filter burrs. This is extremely dangerous for the next level of circuitry. So, if you can use the D trigger, you don't have to latch.
In some places there are no clocks, only latch. For example, now with a CLK to the latch (assuming high-level enable), so the setup time required is the data in the time before the falling edge of the clock, but if it is a DFF, then the setup time is the clock rising along the time required. This means that if the data is later than the control signal, only the latch is used, and this is the case, the latch timing borrow mentioned earlier. Basically the equivalent of borrowing a high-level time. In other words, the latch borrowed time is also limited.
In the If statement and case is not all easy to produce latch, need attention. Via topic which combination of these two codes is more likely to produce latch:
Code 1
[Email protected] (Enable or INA or INB) if (enable) begin Data_out = ina;endelse begin Data_out = Inb;end
Code 2input[3:0] data_in; [Email protected] (data_in) case (data_in) 0: out1 = 1 ' B1; 1,3: out2 = 1 ' B1; 2,4,5,6,7:OUT3 = 1 ' B1; Default: out4 = 1 ' b1;endcase
The answer is that code 2 is more likely to produce latch when combined.
The analysis of the STA of latch is also possible, but it is very familiar to the tool, but it is easy to make mistakes. Currently primetime is supported for latch analysis, and now some integrated tools have built-in STA analysis capabilities, such as RTL compiler, Design compiler. In addition to the ASIC can save resources, latch in the synchronization of the design may be very small, and now the process is mostly placed in the FF to hit a bit.
The latch-level trigger will bring the burr of the input into the output, and the trigger can suppress the input interference because of the edge action.
Latches are often used inside the CMOS chip, but on the PCB board level, it is recommended to use a trigger to lock the data at the clock edge. This is because the data changes will be reflected directly to the output terminal during latch gate opening, so be careful to control the pulse width of the gate signal, and for the trigger, only consider the edge of the clock.
Gate Circuit is the foundation of constructing combinational logic circuit, while latch and trigger are the basis of constructing sequential logic circuit. The gate circuit is composed of transistors, the latch is composed of the gate circuit, and the trigger is composed of a latch. Which is the trigger, the latch--------------the first level is the basis of the latter level. Latches and triggers their output depends not only on the current input, but also on the previous input and output.
The difference between them is that the latch does not have a clock signal, and the trigger often has a clock trigger signal.
The latch is asynchronous, meaning that the output signal changes very quickly after the input signal has changed. On the other hand, many computers are synchronized today, which means that the output signal of all sequential circuits changes simultaneously with the global clock signal. The trigger is a synchronous version of the latch.
Trigger refers to a class of circuit structure, it can be triggered by the signal (such as clock, set, reset, etc.) to change the output state, and maintain this state until the next or another trigger signal came. The trigger signal can be operated with a flat or edge, and the latch is an application type of the trigger.
Seven, d trigger and D latch difference
Clock D trigger is actually a D latch, the edge D trigger is the real D trigger, clock control D trigger in the Enable case output changes with the input, edge trigger only in the case of edge hopping output changes.
Two latches can form a trigger, in the final analysis, the DFF is edge-triggered, and the latch is level-triggered. The output of the latch is transparent to the input, what the input is, the output is what, this is the reason for the latch instability, and the trigger is a master-slave trigger consisting of two latches, the output is opaque to the input, it must be on the rising/falling edge of the clock to reflect the input to the output, it can eliminate the input glitch signal
Eight, the difference between register and latch
The function of registers and latches is to provide data storage and latching.
The storage function refers to storing the data temporarily and removing it when needed. latch function refers to the bus circuit, locking the data output, so that the output does not change with the input terminal.
FPGA Fundamentals 10 (the difference between latches, triggers, registers, and buffers)
