Go UVM Content Synopsis

1. Class: Object-oriented traditional object-oriented programming and the characteristics of SystemVerilog class, definition of class, member and method, constructor, copy of object and deep/shallow copy, parent class/subclass Relation, class inheritance, scope rule, object handle and assignment, method extension and rewrite, local /protected keyword, virtual base class, virtual method, virtual interface.

2. UVM Foundation: UVM History, configurable test components, class library structure, UVM core base class introduction, INCLUDE/MACRO,UVM Transaction (data), basic test component (Testbench components), component phase structure, Trading-level modeling, testcase, Run tests using +uvm_testname command line, UVM test platform run and terminate, objection mechanism.

3. UVM Transaction class transaction/components recommended standard format, Uvm_sequence_item with Uvm_transaction,field micros and field micro flag , transaction (limited) randomization, standard transaction method, method rewrite.

4. UVM Driver class Component (UVM_DRIVER,UVM_SEQUENCER,UVM_AGENT,UVM_ENV), UVM component registration method, interface application in connecting DUT and various components, driving the structure and definition of class components, constructors, The connections for each component.

5. The structure of the UVM Monitor/checker:monitor/checker and its role in the test platform, scoreboard, the application of functioanal coverage.

6. UVM TLM (Transaction level Modeling) TLM Port/export, get/put/transport operation, analysis Port, ' UVM_ANALYSIS_IMP_DECL macros ' use, UVM Practical application of _tlm_fifo.

7. UVM config/factory/callback mechanism config format, Set/get usage rules, Factory mode introduction, UVM Factory mode use steps, Callback mode, callback application in UVM

8. Sequence generation sequence standard form, sequence and sequencer/driver connection, generating data concurrent to DUT, complex sequence cascade, virtual sequence/ Sequencer

9. Register Verification Register Verification basic structure, register model structure, register access mode (front door/back door)

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Go UVM Content Synopsis