How to use make and makefile in Linux: linuxmakefile

How to use make and makefile in Linux: linuxmakefile

What is movie make?

Make is a command tool that explains commands in makefile. It can simplify the commands issued during the compilation process. When you execute make, make searches for the Makefile (or makefile) text file in the current directory and performs corresponding operations. Make automatically checks whether the original code has been changed and updates the execution file.

Why do developers use make?

Assume that a project contains 100 program files. If you want to compile the project, there will be 100 compilation commands. If you want to re-compile, you have to re-compile it as before. This repetitive and tedious work is really unpleasant for us. Therefore, it is not convenient to call gcc indirectly by using make for operations? If we have updated some original code files, make can also take the initiative to determine which original code has been updated with the relevant target file files, and only update this file. This reduces the time required for re-compilation and makes it easier.

What is movie makefile?

Makefile is actually a document that defines a series of rules to specify which files need to be compiled first, which files need to be compiled later, and which files need to be re-compiled, it records detailed information about how to compile the original code! Once the makefile is written, only one make command is required. The entire project is fully automatically compiled, which greatly improves the efficiency of software development.

Let's take a look at the makefile rules:

Target: target file 1 target file 2

<Tab> target file 1 of the gcc-o execution file to be created, target file 2

Target is the information we want to create, and the target file is the relevant object files. The syntax for creating an execution file is the line starting with the <tab> button! Note that the command line must start with the tab button! Its rules are basically as follows:
• # In makefile indicates the annotation;
• <Tab> the first character that needs to be included in the command line (for example, the gcc program command;
• The target and the dependent file (that is, the target file) must be separated by a comma.

The following is an example:

Create three files,

　　

Create a makefile file and write the rules

　　

Now you can use the make command to compile the file. Is this convenient?

　　

If you do not want the compilation rules to be displayed on the screen, you only need to add @ before the rules are written in the makefile ~

What will happen if you compile the file again? Hey, you can try it on your own.

What should I do if I want to clear all the target files and execution files directly by executing a command?

We can define a clean in makefile to execute the rm operation. However, we recommend that you use pseudo targets for operations. The pseudo targets in makefile are declared using. PHONY. When a target is declared as a pseudo-Object

When the rule is executed, make does not try to find the implicit rule to create it. This improves the execution efficiency of make and prevents the clean operation from being executed in the file directory.