I²c and SPI Bus vs. "Turn"

Transferred from: http://blog.csdn.net/skyflying2012/article/details/8237881/

In the last 2 weeks have been debugging IIC and SPI bus equipment, here record 2 kinds of bus, for later forget.

One IIC Bus

The abbreviation for the I2c--inter-ic serial Bus is the inter-chip serial transmission bus introduced by Philips. It achieves duplex synchronous data transfer with 1 serial data lines (SDA) and 1 serial clock lines (SCL). It has the advantages of less interface line, simplified control method, small device package form and high communication rate. In the master-slave communication, there can be more than one I²C bus device simultaneously connected to the I²c bus, through the address to identify the communication object.

IIC interface protocol includes device address information, you can connect multiple slave devices on the same bus, through the answer to exchange data and commands. However, the transmission rate is limited, the standard mode can reach 100Kbps, fast mode can reach 400Kbps (we development Board generally in 130Kbps), high-speed mode to reach 4Mbps, can not achieve full duplex, not suitable for transmitting a lot of data.

The IIC bus is a true multi-host bus that initiates the transmission of multiple hosts on the bus and can prevent data corruption by transmission detection and arbitration.

Learn more about the IIC bus timing:

1.1 Bus data validity

The IIC bus is simplex, so the data at the same time has only one flow, so the sampled effective clock is also single and is high-level sampled data at the SCL clock.

The SDA data on the IIC bus may change at the SCL clock low level, but must be stable at the clock high so that the master and slave devices can sample data according to the clock, such as:

1.2 Bus idle condition

The IIC bus becomes high based on the pull-up resistor, and the SDA SCL is high, after the device on the IIC bus has released the bus (transmission stop is signaled).

1.3 Bus data transfer start and end conditions

IIC bus SCL High level SDA occurs from high to low jump, flag the start of data transmission on the bus condition

IIC bus SCL High level SDA occurs from low to high jump, flag the end of data transmission on the bus condition

1.4 Bus data transmission sequence and ACK response

IIC Bus data room MSB in front, LSB in the rear, from the oscilloscope, read data from left to right

IIC bus transmission of data unrestricted, but each sent to the SDA must be 8-bit, and the host sends 8-bit after the release of the bus, after receiving data from the machine must pull down SDA a clock, the response ACK indicates that the data received successfully, we if the oscilloscope saw the waveform is every 9 bits of data, 8bit+1bit Ack. As follows:

After receiving a byte of data from the machine, if it takes some time to process it, it will pull down the SCL, let the transmission go to the waiting state, process the completion, release the SCL, continue the transfer, as follows:

1.5 Bus read-write timing

The transmission of the data after the starting condition, send a 7-bit slave address, followed by the 8th bit is the data direction (R/W), 0-Indicates the sending of data (write), 1-means to receive data (read). The data transfer is generally terminated by the stop bit (P) generated by the host. But if the host still wants to communicate on the bus, it can produce a duplicate start condition (Sr), and address another slave instead of first producing a stop condition. In this transmission, there may be different combinations of read/write formats.

The IIC Bus master device reads and writes from the device, typically dealing with registers from the device, which can be obtained by reading the datasheet from the device. The bus write timing is as follows:

Master Start + master Addr|w + slave ack + master Reg|w + slave ack + master data + slave ack + master restart. Master Data + slave Nack + master stop

The bus read timing is as follows:

Master Start + master Addr|w + slave ack + master Reg|w + slave ack + Master restart + master Addr|r + slave ack + slave D ATA + Master Nack + master Stop

The difference between the bus read timing and the write is that it takes 2 transfers to complete a read, the first thing to write the register address to the slave device is to write the control register or the command register from the device, and to address the register that is to be operated from within the device.

When I read our BIOS and kernel, we found that the implementation of 2 in the bus read timing is not the same, in the first register address after the write, a hair is restart, a stop, and then start to read the data, the oscilloscope catch waveform found to read the data is correct, This shows that the 2 timings are correct.

IIC Bus Read-write timing is fixed, equipment communication strictly follow the protocol, so the IIC bus device driver programming is relatively simple.

The main application of IIC bus equipment has touchscreen RTC external expansion IO, etc.

Two SPI bus

Spi--serial peripheral Interface, serial Peripheral interface, Motorola company launched a synchronous serial communication mode, is a three-wire synchronous bus, because of its strong hardware, SPI-related software is quite simple, Enables the CPU to have more time to handle other transactions.
SPI usually has a sck clock, STB chip selection, data signal three signals. I²c typically has two signals for SDA data and an SCL clock.

The SPI bus really realizes full duplex data transmission, the SPI has 3 lines and 4 lines two, 4 lines, is more than a line called SDC, used to tell from the device is now transmitting data or instructions. This interface is faster and can transmit more contiguous data. To connect multiple slave devices, the SPI needs to equip each slave device with a single chip signal. If you want to achieve full duplex, you also need to add a data cable (MOSI miso).

This means that the SPI bus is selected from the device through the chip selection.

SPI bus speed is faster than IIC, our Development board can achieve the fastest 30MHZ.

SPI Bus Features:

1. Control mode with master-slave mode (master-slave)
The SPI specifies that communication between two SPI devices must be controlled by the primary device (master) to control the secondary device (Slave). A master device can control multiple Slave devices by providing clock and chip selection (Slave Select) on the Slave device, and the SPI protocol also stipulates that the clock of the Slave device is provided by the Master device via the SCK pin to the Slave equipment, Slave device itself can not produce or control clock, no clock is Slave device does not work properly.

2. Transfer data using synchronous mode (synchronous)
The Master device generates the corresponding clock pulse based on the data to be exchanged (clock pulse), which makes up the clock signal, clock Signal, which controls when the data is delivered between two SPI devices via the clock polarity (CPOL) and clock phase (CPHA) And when the data received is sampled to ensure that the data is transferred synchronously between the two devices.

3. Data exchange (exchanges)
The data transfer between SPI devices is also referred to as Exchange because the SPI protocol specifies that an SPI device cannot act as a "sender (transmitter)" or "receiver" in the data communication process. That is, full-duplex, in each Clock cycle, the SPI device will send and receive a bit size of data, equivalent to the device has a bit size of data is exchanged.
For a Slave device to be able to receive control signals from master, it must be accessed by the master device prior to this. Therefore, the Master device must first select the Slave device through the Ss/cs pin, selecting the Slave device to be accessed.
During the data transfer process, each received data must be sampled before the next transmission. If the previously received data is not read, then the data that has been received will likely be discarded, resulting in the eventual failure of the SPI physical module. Therefore, in the program generally after the SPI transmission of data, to read the data in the SPI device, even if the data (Dummy) in our program is useless.

Specific SPI working principle can see a blog another article

SPI and IIC are 2 different communication protocols, which are now widely used in communication between ICS. And a lot of MCU has been the whole and the SPI and IIC excuses. But like 51 this does not support SPI and IIC microcontroller, can also be used to operate analog clock SPI and IIC communication.

Here is a summary of the 2 kinds of bus similarities and differences:

1 IIC bus is not full duplex, 2 lines SCL SDA. SPI bus for full duplex, 4 wire sck CS MOSI Miso

The 2 IIC Bus is a multi-host bus that locks the device from the address information on the SDA. The SPI bus has only one main device, and the master device is selected by CS chip to determine the device

3 IIC Bus transmission speed at 100kbps-4mbps. The SPI bus transmits faster and can reach more than 30MHZ.

4 IIC Bus Idle state the SDA SCL is high. SPI bus idle state mosi miso It's sck, it's a cpol decision.

5 IIC Bus SCL high normal SDA down along the sign transmission start, rising along the sign transmission end. SPI bus CS Pull low flag transmission start, CS pull high sign transfer end

The 6 IIC bus is an SCL high-level sample. Because the SPI bus is full-duplex, it is along the sampling, depending on the cpha decision. In general, master device is the rising edge of the sck sending, falling edge acquisition

7 IIC Bus and SPI bus data transfer is MSB in front, LSB behind (serial port is LSB in front)

8 IIC Bus and SPI bus clocks are generated by the main device, and only the clock is emitted during data transfer

9 IIC Bus Read and write time series is fixed and unified, the device driver is easy to write. SPI bus different from the device read and write timing difference is relatively large, it must be based on the specific device datasheet to achieve read and write, relatively complex.

I²c and SPI Bus vs. "Turn"