I²c from drive to application (previous)

The I²c (intel-integrated circuit) bus is a two-wire serial bus developed by Phliphs Corporation to connect peripherals and microcontrollers. The application is very extensive, can use in the connection E2rom to save the various interface card, the monitor ROM information, may also use in the BMC to connect various temperature, the voltage, the current and so on the sensor, may also use to connect the memory stripe DIMM, uses to obtain the memory bar the information. SMBus is compatible with i²c, although the signal pin definition is different, but from the software point of view basically can be regarded as I2C,I2C application almost no modification can be run on the SMBus.

Hardware on i²c only two signal lines, data line SDA and clock SCL, through the different phase combination to represent different frames, the starting frame, address data frame, the end frame to form an i²c transmission, the specific timing diagram see below:
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As can be seen from the above figure, when the SCL level is high, the falling edge of SDA indicates that the rising edge of the start S,SDA of an i²c transmission represents the end p of an i²c transmission. At the high level of the SCL per clock cycle, the value of the SDA is sampled sequentially, and then the B1/B2..../B3 is taken as the original data transmitted on the link. The original data transmitted on the link can be divided into three main categories: 1. logical address; 2 logical data; 3. Confirm character. Where the logical address is specified by the device that originated the I²C transmission, the lowest bit of the logical address, specifying the transmission direction of the data: 1 for data from the I²C device read back to the CPU, 0 for data from the CPU write to the I²C device. The logical data can be the data that the CPU sends to the I²C device, or the data that is read back from the I²C device. The confirmation character represents the confirmation frame that I²c returns to the main device from the device. The one-time i²c transfer can read and write one or more bytes, which eliminates the need to reconfirm each transmission of a byte, sequential read and write multiple byte sequence diagram as follows:
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s Addr Rd [a] [data] NA S Addr Wr [A] Data [a] P
The above symbols are defined as follows:
S (1 bit): Start bit
P (1 bit): Stop bit
RD/WR (1 bit): Read/write bit. Rd equals 1, Wr equals 0.
A, NA (1 bit): Accept and reverse accept bit.
ADDR (7 bits): I²c 7 bit address. Note that this can is expanded as usual to
Get a ten bit i²c address.
Comm (8 bits): Command byte, a data byte which often selects a register on
The device.
Data (8 bits): A plain Data byte. Sometimes, I write Datalow, Datahigh
For the bit data.
Count (8 bits): A data byte containing the length of a block operation.
[...]: Data sent by i²c device, as opposed to Data sent by the host adapter.

After understanding the basic timing of the i²c, we have mastered how the I²c controller works. Based on this, in the case of the need to connect the I²C device but the host does not have an I²C controller, you can use two GPIO lines to simulate SDA and SCL, as long as the above i²c sequence, can simulate the behavior of the I²C controller, and then control the I²C device.

According to the sequence diagram above, we can also see that the address bit of I²c has 7 bit (BIT7~BIT1) and the lowest one (BIT0) is a read-write bit. The first 7 bits are from the physical address of the I²C device. The physical address of the BIT7~BIT4 represents the device type, fixed by the equipment manufacturers, different types of coding corresponding to different group, unified by the Http://dlnware.com/theory/I2C-Address-Allocation-Table Convention, For example, the following GROUP9 and GROUP10:
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The physical address of the BIT3~BIT1 is the Address line field, corresponding to the sad, the hardware through the upper and lower resistor fixed, used to distinguish between the different devices connected to the same i²c controller. Since the Address line field has only 3 bits, you can only connect up to 8 i²c devices on the same i²c controller. As an example of reading the SPD controller at the BIOS memory self-test, each DIMM is connected to the CPU's I²C controller, as shown in the SA0/SA1/SA2 signal on different DIMMs:

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Because the DIMM belongs to Group10, the corresponding i²c addresses for the above two DIMMs are: 0xa0,0xa2.
If you need to connect more devices, use the i²c switch. For example, in the BMC that needs to detect multiple temperature sensors and voltage sensors, the i²c switch is often used. As shown in the figure below, you need to use the I²C switch to expand the devices mounted on the i²c:

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One of the A0/A1 is to choose which channel to make. The contents of the control register need to be identified by a reference chip manual. For example, for pca9543a, the implementation is defined as follows:

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Once the above two steps are completed, the link between the device behind the bridge and the I²c controller is established, and the user can access the post-bridge device like a direct access to an I²C device. Of course, access to different i²c devices varies slightly depending on the type of device and the manufacturer's implementation. Some i²c devices require the read-write start address to be sent to the I²c bus, and this offset address can only occupy a byte, at this time if its storage capacity exceeds 2**8=256byte, then this device may have multiple i²c slave device address. Of course, if the offset address allows two byte, as long as the address offset of the access is not more than 2**16byte. In addition, due to the difference in chip implementations, some I²C devices restrict the start address of a continuous read/write to the start address of the on-chip page or sector. But in general, as long as the basic principle of the i²c, but also to notice the specific board and chip differences, we can achieve the control and management of the I²C device.

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I²c from drive to application (previous)