Ii. Arm Exception HandlingThis part is hard to understand.
When an exception interrupt occurs, the system will jump to the corresponding exception interrupt handler after executing the current command. After the exception interrupt processing program is executed, the program returns to the next instruction where the interrupt command is executed. When entering the exception interrupt handling program, you must save the execution site of the interrupted program. When exiting the exception interrupt handling program, you must resume the execution site of the interrupted program.
1. Causes of exceptions
(1) exceptions caused by Command Execution
Software interruption, undefined instruction (including the requested coprocessor instruction that does not exist), prefetch address suspension (memory failure), and data suspension.
(2) External interruptions
Reset, Fiq, and IRQ.
2. Types of abnormal interruptions in arm
(1) reset (reset)
A. When the reset pin of the processor is valid, the system will initiate a reset exception interrupt. The program will jump to the reset exception interrupt handler for execution, including system power-on and system reset.
B. Set the PC to jump to the reset interrupt vector and execute soft reset.
(2) undefined commands
When the ARM processor or the coprocessor in the system deems that the current command is undefined, an undefined command exception interrupt occurs. You can modify the abnormal interrupt mechanism to simulate floating point vector operations.
(3) software interruption
This is a user-defined interrupt command (SWI ). It can be used by programs in user mode to call privileged operation commands. This mechanism can be used in real-time operating systems to call system functions.
(4) prefech abort)
If the prefetch instruction address of the processor does not exist, or the address does not allow access to the current instruction, when the prefetch instruction is executed, the processor causes an exception interruption of the instruction prefetch termination.
(5) Data Access termination (dataabort)
If the target address of the data access command does not exist, or the address does not allow access to the current command, the processor terminates an exception in Data Access interruption.
(6) external interrupt request (IRQ)
When the external interrupt request pin of the processor is valid and the I control bit of the CPSR register is cleared, the processor generates an abnormal interruption of the external interrupt request. A peripheral in the system interrupts the request to process the service.
(7) Fast request interruption (FIQ)
When the processor's external fast interrupt request pin is valid and the F control bit of CPSR is cleared, the processor generates an abnormal interruption of the external interrupt request.
3. Abnormal Response Process
In addition to the reset exception, when an exception occurs, the ARM processor tries its best to complete the current command (except the reset exception) before handling the exception. And execute the following action: (1) Save the address of the next instruction that causes the exception to the R14 in the new mode. If the exception changes from the arm status, the LR register stores the address of the next instruction (current PC + 4 or PC + 8, which is related to the exception type). If the exception changes from the thumb status, then, the offset of the current PC is saved in the LR register. In this way, the exception handler does not need to determine the status from which the exception enters. For example, in case of software interruption exceptions, SWI, mov PC, and r14_svc are always returned to the next command, whether SWI is executed in arm or thumb status.
(2) Save the contents of cpsr to the spsr in which the exception interrupt mode is to be executed.
(3) set the corresponding position of CPSR to enter the corresponding interrupt mode.
(4) Disable IRQ by setting a 7th-bit CPSR. If exceptions occur, they are fast interrupted and reset. Then, set the 6th-bit CPSR to prevent fast interruption.
(5) assign a vector address value to the PC. The ARM processor kernel automatically performs the preceding steps, and the program counter PC always jumps to the corresponding fixed address. If an exception occurs when the processor is in the thumb state, when the exception vector address is loaded into the PC, the processor automatically switches to the arm State, and when the Exception Processing returns, it automatically switches to the thumb state.
4. Exception interrupt handling return/** The content in http://www.mcu16.com/embed/arm/is referenced below **/
After an exception is handled, the ARM microprocessor performs the following steps to return the exception: (1) Restore all modified User registers from the protection stack of the handler.
(2) copy the spsr back to CPSR and send the LR value of the connection register minus the corresponding offset to the PC.
(3) If the interrupt prohibition bit is set during exception handling, clear it here. The reset exception handler does not need to be returned.
5. Program sample analysis
The following is a detailed description of the reset, IRQ, and FIQ processes and implementation methods in Exception Handling Based on the startup code of the ARM7TDMI kernel of Samsung, the following code can be compiled and run in the integrated development environment of Embest IDE and has been verified.
. Text
# In the integrated development environment of Embest IDE, you can link the script file to locate the following statements at the zero starting address and on the system.
# After power-on, the CPU starts to run from here.
Entry:
B resethandler/* 0x00000000; For debug */
B handlerundef/* 0x00000004; handlerundef */
B handlerswi/* 0x00000008; SWI interrupt handler */
B handlerpabort/* 0x0000000c; handlerpabort */
B handlerdabort/* 0x00000010; handlerdabort */
B./* handlerreserved */
B handlerirq/* 0x00000018 */
B handlerfiq/* 0x0000001c */
The above code is used to automatically jump to the corresponding exception handling program based on the number of the CPU according to different situations when an exception occurs, corresponding to seven different working modes of the processor respectively. After the reset, the CPU is transferred to execute the startup code by the zero-address jump command, it is a short assembly language used to initialize special function registers and peripheral circuits inside the CPU and prepare software for advanced language writing before running, this part of assembly code can also be used as a bootloader for embedded systems. After the ootloader code is run, the system application written in advanced languages or the operating system kernel is started. However, it is hard for beginners to understand the interrupt processing in the system startup code.
When the CPU receives the interrupt request signal and allows the CPU to respond to the interrupt request, for FIQ and non-vector IRQ interrupt CPUs, the jump command at 0x0000001c or 0x00000018 is automatically executed according to the work mode set by the interrupt controller. Run
B handlerirq
# Jump
Handlerirq handler handleirq
# The macro-defined action is to jump to the address stored in handleirq to run.
# In the reset initialization code (resethandler), you will see the following:
/* Setup IRQ handler */
LDR r0, = handleirq
LDR R1, = isrirq
STR R1, [R0]
Here we put the isrirq address in handleirq. Therefore, the program will jump to isrirq for execution.
# The ARM7TDMI kernel only supports two interrupt requests: FIQ and IRQ. When multiple interrupt request signals are valid at the same time # The priority is determined by software, then jump to the corresponding interrupted service program. In isrirq, the CPU reads the value of the interrupt suspension register to determine the interrupt source and priority. The integrated Interrupt Controller in provides a more rapid and effective interrupt response method: vector interrupt uses the hardware method of the interrupt controller to directly provide a rapid response to the interrupt service: when multiple interrupt request signals occur, the hardware priority determination logic determines which interrupt request will be responded, at the same time, the hardware logic also uses the jump command in the vector table to directly redirect the CPU to the corresponding interrupt service program entry. This greatly reduces the latency of the interrupt response.
In terms of programming, we need to place the corresponding endpoint addresses of each interrupt request on the corresponding address in the vector interrupt table, such:
Vector_branch:
Ldr pc, = handlereint0/* 0x00000020 */
Ldr pc, = handlereint1/* 0x00000024 */
Ldr pc, = handlereint2/* 0x00000028 */
Ldr pc, = handlereint3/* 0x0000002c */
Ldr pc, = handlereint4567/* 0x00000030 */
Ldr pc, = handlertick/x 0x00000034 */
B.
B.
Ldr pc, = handlerzdma0/* 0x00000040 */
Ldr pc, = handlerzdma1/* 0x00000044 */
......
6. interrupted vector tableHttp://www.mcu16.com/embed/arm/arm593.htm A. The interrupt vector table specifies the correspondence between an abnormal interrupt and its processing program. It is usually stored at the low end of the storage address. In the arm system, the size of the abnormal interrupt vector table is 32 bytes. Each abnormal interrupt occupies 4 bytes and retains 4 bytes of space.
B. A jump instruction or a data access instruction assigned to the PC register is stored in the space of four bytes in the interrupt vector table corresponding to each abnormal interrupt. With these two commands, the program will jump to the corresponding exception interrupt handling program for execution.
C. When several abnormal interruptions occur at the same time, the system cannot handle these exceptions in a certain order. For example, when FIQ, IRQ, and the third interrupt occur simultaneously, FIQ has a higher priority than IRQ, and IRQ ignores it until FIQ returns to the user code.
The interrupt vector address of each abnormal interrupt and the priority of interrupt handling
--------------------------------------
Interrupt vector address | abnormal interrupt type | abnormal interrupt mode | priority (6 lowest) |
--------- | -- ------ | --------- | ---- ----- |
0x00 | reset | privileged mode | 1 |
0x04 | undefined command | und termination mode | 6 |
0x08 | software interruption | privileged mode | 6 |
0x0c | command prefetch terminated | termination mode | 5 |
0x10 | Data Access terminated | termination mode | 2 |
0x14 | reserved | not used |
0x18 | external interrupt request | IRQ mode | 4 |
0x1c | fast request interruption | FIQ mode | 3 |
--------------------------------------
7. Summary
B0 uses two vector meters to efficiently and reliably handle exceptions, master the exception pattern of the microprocessor, and respond to the reset, Fiq, and IRQ in exception handling, this helps us to understand the operating principle of the ARM7TDMI kernel for exception handling, and helps us to understand the startup code (or bootloader) ), it can also make more effective use of the hardware resources of the chip to write streamlined and efficient embedded program code. It will be of great help to the overall design of the embedded system and is the basis for embedded system development.
