IIC timing details

AT24C02 is provided by ATMEL, iic bus serial EEPROM (electronic eraser programmer read only memory). Its capacity is 2 kbit (256B) and its operating voltage is between 2.7 v "5.5v, the production process is CMOS.



Generally, digital chips are GND and VCC in the lower left and upper right corner. Capacity Calculation Method: AT24Cxx: 01 "1024
Capacity = xx * 1 kbit.

Write process:

The fixed part of the AT24C-series EEPROM chip is 1010, A2, A1, and A0 pins connected to the high and low levels to obtain the Three-bit encoding. The 7-bit encoding is the address code of the device.

When the MCU performs write operations, it first sends the 7-bit address code of the device and the Write direction bit "0" (a total of 8 bits, that is, one byte ), after sending the message, the SDA line is released and 9th clock signals are generated on the SCL line. After confirming that the selected memory device is its own address, a response signal is generated on the SDA line as a response. After receiving the response, the MCU can transmit the data. When transmitting data, the microcontroller first sends the first address of a byte written into the memory. After receiving the response from the memory device, the microcontroller sends the data byte one by one, however, after each byte is sent, the system waits for a response. The address in the AT24C series is automatically added with 1 after each Data byte address is received. In the chip's "one-time loading Byte Count" limit, you only need to enter the first address. When the number of bytes loaded exceeds the "number of bytes loaded at a time" of the chip, the data address will be "mounted" and the previous data will be overwritten.




Byte write:




Page writing:



Read process:

The microcontroller first sends the device's 7-bit address code and the Write direction bit "0" ("pseudo write"). After sending the code, the SDA line is released and 9th clock signals are generated on the SCL line. The selected memory device generates a response signal on the SDA line after confirming that it is its own address.

Then, send a byte to read the first address of the device's storage area. After receiving the response, the microcontroller must repeat the start signal and send the device address and read direction ("1 "), after receiving the device response, you can read the data bytes. Each time you read one byte, the microcontroller must reply to the response signal. When the last byte of data is read, the microcontroller should return a "non-response" (high level), and send a termination signal to end the reading operation.



Current address read:




Random read:




Sequential read:




IIC bus simulation sequence diagram:



Iic bus response sequence diagram:



Device address:



Write cycle:



There must be a 10 ms twR interval between two writes.