Implementation of the algorithm based on Dsp_builder on FPGA

I. Summary

The FPGA implementation of the algorithm is combined with dsp_builder, Matlab, Modelsim and Quartus II software.

Second, the experimental platform

Hardware platform: Diy_de2

Software platform: quartus ii9.0 + modelsim-altera 6.4a (quartus II 9.0) + dsp_builder9.0 + matlab2010b

Iii. preparation of the software platform 1, software matching

Based on Altera's official documentation, you can see version matching information for Quartus II, Modelsim, Dsp_builder, and Matlab. As shown in 1.

Http://www.altera.com/support/ip/dsp/ips-dsp-version.html

Figure 1 Software version Matching

In general, the Quartus II, Modelsim, and Dsp_builder versions must match, and the MATLAB version is higher than the prescribed version, but it is possible that some modules will not be available for this to happen.

2, the installation of software

Installation and crack Dsp_builder The steps can be see "The Wind Drunk Moon" classmate's article, links as follows:

DSP Builder Installation Guide (take 9.1 for example)

It should be stated that:

The version of MATLAB for the dsp_builder9.0 version should be 2007b, and my 2010b, although compatible, but there are still some problems, such as some components of the advanced library can not be displayed, 2 is shown. The best solution is to match the version exactly as recommended.

Figure 2 Some features are not available

Iv. Examples of routine

A sine wave routine is used to illustrate the flow of dsp_builder. Can see pan song "Eda Technology and VHDL" (3rd Edition) 9th chapter of the routine.

1. Establish Simulink Design Model

In Matlab, a new Simulink model is created, as shown in 3.

Figure 3 The Simulink model established

2. Simulink model Simulation (system level, i.e. algorithm level)

After setting the parameters, run the simulation, double-click scope to see the simulation waveform, 4 shows.

Figure 4 Simulink Simulation waveform

3. How to use Signalcompiler

After simulation verification is done in Simulink, the design needs to be transferred to the hardware for implementation. This is the most critical step in the entire DSP builder design, whereby the VHDL RTL code for FPGA can be obtained. As shown in 5.

Figure 5 Signalcompiler

4. RTL-level simulation using Modelsim

This step is actually a simulation of the VHDL files converted by. mdl files, which can be implemented by adding testbench components. As shown in 6.

Figure 6 Testbench

In addition, Launch GUI selection, tick, then directly start the Modelsim simulation; if unchecked, you can modelsim the Tcl-->execute Macro under the Tools menu ... Find the Sinwave_add.tcl file under the project folder for emulation.

5. Using Quartus II for timing simulation

The previous step is functional simulation, which is pre-simulation in Modelsim. This is to further verify that the timing simulation is correct or not, that is, post-simulation. This step requires a few notes:

(1) Quartus II 9.1 software comes with a simulation component, and then the software no longer contains this component.

(2) Modelsim can be used to realize the simulation and verify the timing simulation.

6. FPGA verification

Download the design to the FPGA for verification. Verify that the waveform is correct through the oscilloscope.

V. Summary

The above process involves the specific use of the various parts, you can refer to Altera's Dsp_builder official documentation.

Dsp_builder's introduction: Http://www.altera.com.cn/literature/hb/dspb/hb_dspb_intro.pdf

Basic Library of Dsp_builder: http://www.altera.com.cn/literature/hb/dspb/hb_dspb_std.pdf

Dsp_builder's Premium Library: http://www.altera.com.cn/literature/hb/dspb/hb_dspb_adv.pdf

Reprinted from: http://www.cnblogs.com/sunev/archive/2012/11/17/2774836.html

Implementation of the Dsp_builder-based algorithm on the FPGA