In single-port RAM.

Today, we finally have some small gains. Really good.

About this configuration. You can clearly understand how to configure it through the 28th tutorial on FPGA video series. Now I paste the sample file and test file.

 

First, let's look at the waveform chart generated by quartuⅱ.

 

Paste it with no CLR signal. Easy to use.

// 'Include "ram4.v" // do not use module RAM (CLK, RST, ram_wr, ram_addr, data_in, data_out); input CLK, RST, ram_wr; input [] ram_addr; input [] data_in; Output [] data_out; // ram4 U1 (. address (ram_addr ),. clock (CLK ),. data (data_in ),. wren (ram_wr ),. q (data_out); endmodule

 

Let's talk about it. It carries the CLR signal.

//`include "RAM4.V"module RAM(CLK,RST,RAM_WR,RAM_ADDR,DATA_IN,DATA_OUT);input CLK,RST,RAM_WR;input [7:0]RAM_ADDR;input [7:0]DATA_IN;output [7:0]DATA_OUT;//RAM4 u1(.aclr(CLR),.address(RAM_ADDR),.clock(CLK),.data(DATA_IN),.wren(RAM_WR),.q(DATA_OUT));endmodule 

 

The test file is as follows:

'Timescale 1ns/100 psmodule a_ram_tb; Reg CLK, RST, ram_write; Reg [] ram_addr; Reg [] data_in; wire [] data_out; Ram ram4k (. CLK (CLK ),. RST (RST ),. ram_wr (ram_write ),. ram_addr (ram_addr ),. data_in (data_in ),. data_out (data_out); initial beginclk = 0; forever #5 CLK = ~ CLK; // 200 m 5 nsendinitial forever @ (posedge RST) beginram_write = 0; ram_addr = 8 'hzz; data_in = 8 'hzz; endinitial beginrst = 1; ram_write = 0; ram_addr = 8 'hzz; data_in = 8 'hzz; #500; rst = 0; ram_write = 0; ram_addr = 8 'hzz; data_in = 8 'hzz; #1000; task_ram_write (8 'd0, 8 'd1); // 0 address write data 1task_ram_write (8 'd1, 8 'd3); // 1 address write data 3task_ram_write (8 'd2, 8 'd5); // 2 address write data 5task_ram_write (8 'd3, 8 'd7); // 3 address write data 7 #50; @ (posedge CLK ); ram_addr = 8'd0; // read address 0 Data @ (pose Dge clk); ram_addr = 8'd1; // read address 1 Data @ (posedge CLK); ram_addr = 8'd2; // read address 2 Data @ (posedge CLK ); ram_addr = 8'd3; // read address 3 data #100; $ stop; endtask task_ram_write; // two parallel blocks in sequential control are input [] ADDR; input [] data; begin // two statements executed sequentially. Write Data first, then read @ (posedge CLK); fork // execute ram_write <= 1; data_in <= data; ram_addr <= ADDR; join @ (posedge CLK) in parallel ); // read data operation fork // execute ram_write in parallel <= 0; data_in <= 8 'hzz; // configure the address and clock line as high-impedance// Ram_addr <= 8 'hzz; // This statement is very important.Joinendendtaskendmodule

This shows the difference between blocking this statement (top) and blocking this statement (bottom.

 

 

 

Now you know the answer.// Ram_addr <= 8' hzz; this statement is used. It took a long time to block this sentence. (It's also strange that my foundation is not solid .). It's time to go to bed.