I²c Bus

2. Overview:

   I²C is the abbreviation for inter-integrated Circuit, pronounced as "eye-squared cee" or "Eye-two-cee", which is a two-wire interface.

   I²C uses only two bidirectional lines, one Serial Data line (SDA) and the other Serial Clock (SCL).

   SCL: The rising edge enters data into each EEPROM device, and the falling edge drives the EEPROM device output data. (Edge Trigger)

   SDA: Bidirectional data line, for OD gate, with any number of OD with OC Gate into "line with" relationship.

4. Output stage

   The SDA, SCL PIN circuit structure is the same for each i²c bus device, and the output drive of the PIN is connected to the input buffer. wherein the output is open-drain FET, the input buffer is a high input impedance of the same phase, the circuit has two characteristics:

   1) Since SDA, the SCL is the open-drain structure (OD), so they must be connected with a pull-up resistor, the resistance is usually 1k8, 4k7 and 10k, but 1k8 the best performance, when the bus is idle, two lines are high. The low level of the output of any device connected to the bus will lower the signal of the bus, that is, the SDA and SCL of each device are both line "and" relationship.

   2) pin in the output signal at the same time, the level on the PIN to detect whether the same as the output, for "clock synchronization" and "Bus quorum" provides a hardware basis.

6. Master devices and slave devices

   All peripheral devices in the system have a 7-bit "slave-device address code", where the high 4 bits are the device type, developed by the manufacturer, and the lower 3 bits define the address for the device pin, defined by the user. The main control device through the address code to establish the mechanism of multi-machine communication, so that the I²C bus eliminates the peripheral parts of the chip line, so that no matter how many devices connected to the bus, its system is still a simple second-line structure. Terminal mount on the bus, there is the main and slave points, the main end must be a logical module with the CPU, on the same bus at the same time to have a master, can have multiple from the end, the number of the slave is limited by the address space and the maximum capacitance of the bus 400pF.

• • The main terminal is used to drive SCL line;
  • Responding to the main device from the device;

Both can transmit data, but the transmission cannot be initiated from the device, and the transmission is controlled by the master device.

4. Rate:

Normal mode: 100kHz;

Quick mode: 400kHz;

High-speed mode: 3.4MHz;

There's no need to use a high-speed SCL, keep the SCL at 100k or below, and forget about it.

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• Start signal: When the SCL is high, the SDA jumps from high to low, and the start signal is a level-hopping timing signal, not a level signal.
• Stop signal: When the SCL is high, the SDA jumps from low to high, and the stop signal is also a level-hopping timing signal, not a level signal.

3.ACK

Each time the transmitter sends a byte, it releases the data line between the clock pulses 9, and the receiver feeds back a response signal. When the response signal is low, it is specified as a valid answer bit (ACK short answer bit), indicating that the receiver has successfully received the byte, the response signal is high, the specified non-response bit (NACK), generally indicates that the receiver received the byte is not successful. The requirement for a feedback effective answer bit ACK is that the receiver pulls the SDA line low during the low level before the 9th clock Pulse and ensures a stable low level during the high level of the clock. If the receiver is a master, after it receives the last byte, it sends a NACK signal to notify the controlled sender of the end of data transmission and releases the SDA line so that the master receiver sends a stop signal p.

such as the sampling result of the logic Analyzer: After releasing the bus, if there is no answer signal, SDA should continue to be high, but the middle blue dotted section shows that it is pulled low low level, proof received a response signal.
The two messages we have here are: 1) The receiver pulls down the sda;2 during the low level before the rising edge of the SCL) the answer signal remains at the end of the falling edge of the SCL, as noted in the red logo above.

My understanding: Although only required to remain stable during high levels, there is a pre-order, that is, the data should be ready before the rising edge of the SCL, because the data is entered into the device (EEPROM) on the rising edge of the SCL, as noted in the---Overview of the preceding I²c bus.

5. Transfer of data:

Each bit of data transmitted on the I²C bus has a clock pulse counterpart (or synchronous control) that transmits each bit of data sequentially on the SDA, in conjunction with the SCL serial clock. The transmission of data bits is an edge trigger.

Second, the work process

All traffic on the bus is raised by the master. In a single communication, the main controller and the controller are always playing two different roles.

1. Primary device sends data to slave device

The primary device sends the start bit, which notifies the bus that all device transmissions begin, and then the host sends the device address, and the slave that matches this address will continue the transfer process, while the other slave will ignore the next transmission and wait for the next transmission to begin. The primary device addresses the internal register address of the slave device to which it is to be read or written after it is addressed to the slave device, and then the data is sent. After the data is sent, the send stop bit:

The writing process is as follows:

Send starting Bit

• Send the address and read/write selection bits from the device, release the bus, wait until the EEPROM pulls down the bus to answer it, or if the EEPROM receives a successful response, the EEPROM does not generate an answer if there is no successful handshake or if the data sent is wrong, then a resend or termination is required.
• Send the internal register address that you want to write, and the EEPROM responds to it;
• Send data
• Send Stop bit.
• When the EEPROM receives a stop signal, it enters an internal write cycle, which is approximately 10ms, and any operation will not be answered by the EEPROM; (so a delay is inserted between the two writes in this way, otherwise it will cause failure, the blogger had a little pit here)

With:

Need to explain is: ① the main controller through the sending address code and corresponding to the control set up a communication relationship, while the other connected on the bus is also received the address code, but because it does not correspond with its own address, so early exit and the main controller communication;

2. The process by which the master reads the data:

The process of reading is more complicated, and before you can read the data from slave, you must first tell it which internal register you want to read, so you must write it first (dummy write):

• Send start bit;

• Send slave address +write bit set;

• Send internal register address;

• Resend the starting bit, i.e. restart;

• Resend slave address +read bit set;

• Reading data

• Send Stop bit

I²c Bus