I²c-Interface Learning Summary

1. IIC Bus Concept:
A, only two bus lines: a serial data cable, a serial clock line.
b, each device connected to the bus can use the software according to their unique address to identify.
C, the transmission of data between the device is a simple master-slave relationship.
D, host can be used as host transmitter or host receiver.
E, it is a true multi-host bus, two or more hosts simultaneously initiating data transmission, can be through conflict detection and arbitration to prevent data corruption.
F, serial 8-bit bidirectional data transmission, bit rate in the standard mode up to 100kbit/s, in the fast mode up to 400kbit/s, in high-speed mode can reach 3.4mbit/s.
G, on-chip filter can increase anti-jamming ability, ensure the integrity of the data.
H, the number of IIC connected to the same bus is limited only by the maximum capacitance of the bus 400pF.
2, the type of the IIC bus signal:
Start Signal (S): When the SCL is high, SDA jumps from high to low to start transmitting data.
End Signal (P): When the SCL is high, SDA jumps from low to high and ends the data transfer.
Response Signal (ACK): After receiving 8 bits of data, the receiver pulls down the SDA level in the 9th clock cycle.
3. IIC Bus Data transmission format:
1. Each byte sent to SDA must be 8 bits, and the number of bytes sent per transmission is unrestricted.
2, each byte must be followed by a response bit.
3, A: The host first issued S signal, B: then issued 8 bits of data, the 8 bits of data in the first 7 is the address of the slave, the 8th bit represents the direction handed down (0, the write operation, 1, the read operation) C: The selected slave sends a response signal, and then transmits a series of bytes and their response bit. D: The host sends a P signal to end the transmission.
4, s3c2440 Bus Controller:
1. Iiccon Register: Controls whether an ACK signal is emitted, sets the transmitter's clock, opens the IIC interrupt, and identifies whether the interrupt occurred.
2, Iicstat Register: Select the IIc interface mode, emit s signal, p signal, enable the Receive/Send function, and identify various states, such as the success of the arbitration? Are they addressed as slave machines? Did you receive the 0 address? Is the ACK signal received?
3, Iicadd Register:
4, Iicds Register: Send and receive data.
5, s3c2440 host transmitter workflow:
1. Start
2, configure the host Transmitter IIC initialization function Program implementation
3. Write the slave address to iicds Iicds = slvaddr; Slvaddr from the device address
4, write 0xf0 in Iicstat, start transmission iicstat = 0xf0;
5, Iicds in the data is sent out on the s3c2440, after the start, as long as the Iicds inside the data will be automatically sent out
6, after the response cycle occurs after the data in the sending Iicds is completed, the last one is the ACK response bit automatically generated sent out, jump to interrupt function, execute interrupt function
7, if no data to send, then jump to 11, otherwise jump to 8 to determine whether the current work is completed, choose Next
8. Write the next data to be sent to iicds Iicds = data;
9, recover IIC transmission iiccon = 0XAF; 0xaf value for Recovery IIC Transport configuration value
10, Iicds in the data is sent out on the s3c2440, after the start, as long as the Iicds inside the data will be automatically sent out
11, write 0xd0 in Iicstat, stop transmission iicstat = 0xd0; 0xd0 value for stop transfer configuration value
12, clear interrupt jump to interrupt function, execution stop interrupt, SRCPND = BIT_IIC;INTPND = BIT_IIC;
13, wait for the p signal to delay, delay (10000); function execution
14. End
6, One: EEPROM chip introduction

In this analysis at24c02a/at24c04a/at24c08a, for other different models of EEPROM chip to be based on the specific manual analysis. Their size is 2K (256*8)/4k (512*8)/8k (1024*8) so it can be seen that the actual size is 256/512/1024byte. The three-bit address line for at24c02a is dead, because the 8-bit address is sufficient for read and write operations, so the three-bit address line is dead as a slice, and the first bit of the three-bit address line for at24c08a must be written dead, and the last two bits can be used as the internal page address. Because the size of the at24c08a exceeds the 256byte,8 for addressing, it is impossible to use all the space in the chip. Therefore, the following two bits can be determined by the program.

There are two types of write EEPROM, (when writing data, AMR9 as the main device, EEPROM is slave device)

The first type of write byte:



Writing a byte actually requires three data to be sent. In this process, the primary device is sent status. First Data--the device address. The second data--arm9 the address in the EEPROM that you want to write. The third data-the specific data that you want to write to the EEPROM. Last stop.

The second way to write a page:



Self-feeling actually write page and write byte should be consistent, first data--device address. The second data--arm9 the address in the EEPROM you want to write (but this address is the first address.) AT24C02 one page is 8byte,at24c04/08 one page is 16byte. So when you write a page up to the size of a page, if too much of it will start again from the first address, previously written will be overwritten. ）。 Third to fourth ... Data--is the data you want to write to the EEPROM. Last Stop

Read the data in the EEPROM

The first reading of the current address data



The main device is still ARM9, from the device is the EEPROM, but pay attention to the state of the main device, sometimes it is sent status, sometimes it is the receiving State

The first data--(the main device is now in a state of occurrence) sends the slave address and configures the primary device to receive status.

The second data--(the main device is in the receiving State) ARM9 receive data, note that there is no ACK at this time. Stop again. (to read the data after generating no ACK, the data will be stable.) Online have asked why in reading the IIC last need to read two times, I myself experiment, only need the last time on the line,)

The second method of random read data



The first data--(the primary device is in a state of occurrence), sends a slave address. The first device address is used to match from the device, also known in the document as a "dummy" byte write sequence

The second data--(the main device is in a state of occurrence), sends an address that wants to read the data in the EEPROM.

The third data--(the main device is in a state of occurrence), sends a slave address. This is the specific requirement for sending this: (where the primary device is configured to receive state), this sending device address is used to simultaneously adjust the state of the master device.

The fourth data-the data that needs to be read (the main device is in the receiving State). is also a no ACK, similar to reading the current address. and finally stop.

The third type of read-sequence address



Somewhat similar to reading the current data.

The first data--(the primary device is in the sending state), issues the device address, and configures the primary device to receive status. Receive data preparation for the back

Second to third ... The number of data-(the main device is in the receiving state), each of the preceding messages will send an ACK, and the last data is a no ACK.

Stop again.

Above, the main equipment to pay attention to the adjustment of the State, and no ACK when the processing, the following case procedures, can be more clearly see how to deal with.


Second, in the s3c2440 for the IIC need to configure the Register

Gpecon, the main is to configure this gpio as IIC mode.

Iiccon: Wherein [0]---[3] together with [6] determine the clock frequency of the IIC bus.

[4] is an interrupt flag bit, if we do not use the interrupt mode, it should be possible to query this one. (I use the interruption, no specific own practice)

[5] IIC interrupt Enable. [7] Whether to send an ACK. This one should pay attention to the changes when reading the data in the back.

Iicstat: This register is mainly a number of flags, do not need to configure, the main configuration is the few.

[4] enable the IIC data line, so that it can send data.

[5] Start and stop iic,1 start. 0 stop.

[6-7] is the state of the configuration AMR9, the general CPU is the role of a master device. Only when the two CPUs are communicating with each other can it be configured to be a slave device state. So in our experiment, ARM9 is all in the role of the main device.

Iicadd is the CPU to do from the time of the device, give him the configuration from the device address, here can not be configured.

IICDS: Data shift register. Sending data is the data sent to this register. To receive data is to fetch data from this register.

If you use interrupts, of course, you have to configure Intmsk to open the IIC interrupt.



Three: IIc successfully read and write EEPROM program

First, there are a few notes to the program:

The 1:ack must be a volatile type because the value is changed in the interrupt, otherwise the value is saved in the cache, and the value is not actually read when it is last detected.
2:IIC interrupts are always in the ACK cycle, generated, I did not post the Operation Flowchart, ARM9 document in the IIC this chapter has been clearly given. So in the ACK of those data sent and received can be interrupted operation, but from the reading data after receiving data, because it is no ACK, so there is no interrupt operation, and self-made a delay. Reading the data.

void Test_iic (void)
{
unsigned int i,j,save_e,save_pe;
Static U8 data[256];

uart_printf ("\niic Test (Interrupt) using at24c02\n");

Save_e = Rgpecon;
Save_pe = Rgpeup;
Iic_init ();//initialization of some registers required for IIC
uart_printf ("Write test data into at24c02\n");

for (i=0;i<48;i++)
wr24c080 (0xa0,i,i);//slvaddr, addr, data


for (i=0;i<48;i++)
Data[i] = 0;

uart_printf ("Read test data from at24c02\n");

for (i=0;i<48;i++)
rd24c080 (0xa0,i,& (data[i));

Line changed 0 ~ F
for (i=0;i<3;i++)
{
for (j=0;j<16;j++)
uart_printf ("%2x", Data[i*16+j]);
uart_printf ("\ n");
}
Rintmsk |= BIT_IIC;
Rgpeup = Save_pe;
Rgpecon = save_e;
}



void Iic_init (void)
{
Configuring the GPE port for IIC function
Rgpecon &=~ (0xf<<28);
Rgpecon |= (1<<31) | (1<<29);
Generates ACK,IIC interrupt enable, frequency 200KHz
Riiccon = 0;
Riiccon |= (7) | (1<<5) | (1&LT;&LT;7);
Mode is the primary send, enabling RX/TX (either read or write initialization to be sent primarily)
Riicstat |= (3<<6) | (1&LT;&LT;4);
Riicadd = 0x10;//represents 2440 as the address from the device when it is from the address,
Here 2440 is present as a master device, so it has no effect.
The EEPROM identifier is 1010
Control byte, where the high four bits are the device type identifier, and the latter three bits are selected as the chip
The last one decides to read and write, 0 is read, 1 is written.

IIC transmission interrupt is turned on
rintmod=0x0;
Rintmsk &=~BIT_IIC;
PISR_IIC = (unsigned) iicint;
}



[wr24c080]****************************
void wr24c080 (U32 slvaddr,u32 addr,u8 data)
{
F_getack = 0;
Riicds = slvaddr;//sends the first data
Riicstat = 0xf0;
while (F_getack = = 0);//wait for Send to end
F_getack = 0;
Riicds = addr; Send a second data
Riiccon = 0xaf;
while (F_getack = = 0);//wait for Send to end
F_getack = 0;
Riicds = data; Send a third data
Riiccon = 0xaf;
while (F_getack ==0); Wait for Send to end
Riicstat = 0xd0; Stop IIC
Riiccon = 0xaf;
Delay (3);
}



void rd24c080 (U32 slvaddr,u32 addr,u8 *data)
{
Char Crecvbyte;

F_getack = 0;

Riicds = slvaddr; Send First Data
Riicstat = 0xf0;
while (f_getack==0); Wait for the end
F_getack = 0;
Riicds = addr; Send a second data
Riiccon = 0xAF;
while (f_getack==0); Wait for the end
F_getack = 0;
Riicds = slvaddr; Send a third data
Riicstat = 0xb0;//Configuration Master device status for receive
Riiccon = 0xaf;
while (f_getack==0);//wait for the end
F_getack = 0;
Riiccon = 0x2f; No ACK configuration, no ACK signal is sent after receiving data
Delay (2); Wait for its stability, delay does not require precise
Crecvbyte = riicds;//receives fourth data
Riicstat = 0x90; Stop IIC
Riiccon = 0xaf;
Delay (3);
*data = Crecvbyte;
}



void __irq iicint (void)
{
Clearpending (BIT_IIC);
F_getack = 1;
}

Sentiment:
1, in the embedded development about the Bus protocol class, need to look at the bus protocol to send the receiving process operation, again is to look at the host (or directly CPU) of the document, understand its operating principles and processes, and then look at the document from the machine, operating principles and processes, and finally began to use code to docking.
2, must pay attention to the use of structural body and keyword volatile, as far as possible to separate each small function for the function to write.
3. Must know which actions in the process are automatically completed? What do I need to do to configure setup with code?
4. Note the use type of the function variable.
5, try to use multiple files to declare variables and functions.
6, all and hardware-related addresses it is best to use the macro definition in the. h file to define a new name, usually in uppercase letters.
7, in the RTC clock settings, you need to send a lot of data at the same time, you can use the structure, arrays, add or subtract from the implementation. When writing EEPROM, write function requires three parameters, need to send data more than once, note the need to restore the ACK value after sending, resume IIC transmission.
8, in the program using the tag ACK variable, such as: while (ack = = 0), when entering the loop, always in the loop, the data is in the transmission process, until the completion of the response period will be interrupted, and then jump to interrupt execution, the ACK is marked as 1, at this time, the loop stops. If you do not wait for the data transfer to complete, the next sentence will be executed shortly, and the data may not have been completely sent.
9, if it is time to write a page, you need to send several times, data three ... Data four ... Data Five ... It then ends the transmission because the IIC bus transmits only 8 bytes at a time, and the previously entered address is the first address.
10, one time to read a page, with an array to receive, read more several times, address to self-add, so that you can read a number of data.

I²c-Interface Learning Summary