JTAG TAP Controller

The TAP controller is a synchronous finite state machine that responds

To changes at the TMS and TCK signals of the TAP and controls the sequence of operations of the circuitry.

TAP Controller State diagram

* Yellow * Status can be repeated, other states can only occur once, the next TCK rising Edge will switch to the next state.

State descriptions

Reset

The test logic is disabled so, normal operation of the chip logic can continue unhindered.

No matter in which state the TAP controller currently are, it can change to Reset state if TMS are high for at least 5 CLO CK cycles.

As long as TMS is high, the TAP controller remains in Reset state.

Idle

Idle is a TAP controller state between scan (DR or IR) operations.

Once entered, this state remains active as long as TMS are low.

Dr-scan

Temporary controller state. If TMS remains low, a scan sequence for the selected data registers is initiated.

Ir-scan

Temporary controller state. If TMS remains low, a scan sequence for the instruction register is initiated.

Capture-dr

Data may is loaded in parallel to the selected test data registers.

SHIFT-DR

The test data register connected between TDI and TDO shifts data one stage towards the serial output with each clock.

Exit1-dr

Temporary controller state.

PAUSE-DR

The shifting of the test data register between TDI and TDO is temporarily halted.

Exit2-dr

Temporary controller state.

Allows to either go-to-shift-dr state or go-to-update-dr.

Update-dr

Data contained in the currently selected data register is loaded to a latched parallel output (for registers that has s Uch a latch).

The parallel latch prevents changes at the parallel output of these registers from occurring during the shifting process.

Capture-ir

Instructions May is loaded in parallel into the instruction register.

Shift-ir

The instruction register shifts the values in the instruction register towards TDO with each clock.

Exit1-ir

Temporary controller state.

Pause-ir

Wait state, that temporarily halts the instruction shifting.

Exit2-ir

Temporary controller state. Allows to either go-to-shift-ir state or go-to-update-ir.

Update-ir

The values contained in the instruction register is loaded into a latched parallel output from the Shift-register path.

Once latched, this new instruction becomes the current one.

The parallel latch prevents changes at the parallel output of the instruction register from occurring during the shifting Process.

JTAG TAP Controller