Learning FPGA100 A noteworthy point (reproduced)

1.FPGA is not a programming language, but is a comprehensive hardware description language.
2.Verilog supports both process initial and always processes
3. Blocking vs. non-blocking refers to the process itself.
4. Circuit type using process module: Combined circuit-----sensitive to all inputs used in combinational logic
Example:
[Email protected] (A or B or sel)
Timing circuit-----Sensitive to clock and control signals only
Example: Always @ (Posedge CLK or Negedge CLR)
5. You can use the case statement to complete the function of a multi-channel selector.
There are two types of subroutines in 6.verilog:
Functions and Tasks
Function-----Returns a value based on the input
-----Generating Combinatorial logic
-----used in Expressions: Assign Mult_out=mult (INA,INB);
-----function is a combination of logic and cannot contain any delay, event, or timing control declaration, with at least one input variable
Always returns a variable
-----can call a function, but cannot invoke a task.
Task-----can be a combination or a register
-----invoke the task in the form of a declaration: Stm_out (Nxt,first,sel,filter);
-----Similar to tasks in other programming languages
-----Different tasks do not need to pass arguments, and functions pass parameters
-----can invoke tasks and functions.
-----can contain any delay, event, or timing control declaration
-----returns 0 or more values
7. An integrated subset of Verilog syntax refers to the syntax that can be implemented with hardware. Strive to use the simplest language to achieve the most complex hardware circuit.
8. The hardware has the corresponding input and output interface, either the input or the output, or the input and output.
Model 9.reg refers to the combination of logic inside a storage data, wire is a combination of logic inside a line.
Define defines a parameter that is effective throughout the project. A parameter defined by the parameter
Applies only in this file.
11. A variety of logical operators, shift operators, arithmetic operators are mostly class synthesis.
12.assign is generally only for combinatorial logic, and the always statement can be used for both combinatorial logic
can also be used for timing logic, the sensitive table of the always module, or the combined logic if it is level
If it is along the signal Posedge or Negedge is the timing logic.
13.begin-------End is similar to the {} in the C language.
14.for Statement-----Loop Because the combined results could be a waste of resources.
So it is generally used less, but in some specific design can play
A multiplier effect.
A total of logic units consumed by the 15.total logic element.
16. Behavioral-level simulations can be understood as functional simulations (pre-simulation), and post-routing simulations can be understood as timing simulations (post-simulation)
17. The first very good code to write is as follows: notice why Clk_div_r and CNT are defined as Reg-type, and what the corresponding meaning is
Module Clkdiv (
Clk,rst_n,
Clk_div
);

Input CLK; 50MHz
Input rst_n; Low-Power Reset signal

Output clk_div; Crossover signal, connected to buzzer

//---------------------------------------------------
REG[19:0] CNT; Divider counter

Always @ (Posedge CLK or Negedge rst_n)//Asynchronous Reset
if (!rst_n) CNT <= ' D0;
else CNT <= cnt+1 ' B1; Register CNT 20MS Cycle count
//----------------------------------------------------
Reg Clk_div_r; Clk_div Signal Value Register

Always @ (Posedge CLK or Negedge rst_n)
if (!rst_n) clk_div_r <= 1 ' b0;
else if (cnt = = hfffff) clk_div_r <= ~clk_div_r; Let Clk_div_r value flip once per 20ms

Assign clk_div = Clk_div_r;

Endmodule

18. Clock and reset signals are required in the timing logic.
19. Note that a problem with wire assignment is as follows: wire[2:0] key_an=key_rst_r& (~key_rst)
It is equivalent to one of the following assignment statements
WIRE[2:0] Key_an;
Assign key_an=key_rst_r& (~key_rst);
The effect of the implementation is the same. This method is: Pulse edge detection method
20. In practice, in addition to describing the simulation test excitation (testbench) with a For loop statement,
A For loop is rarely used in RTL encoding because the For loop is expanded by the aggregate into all variable conditions
, each variable occupies a register resource, and cannot effectively reuse the hardware logical resources.
Cause a huge waste. Generally used case statements instead.
The FPGA general trigger resource is rich, and the CPLD logical resource is richer.
22. Asynchronous circuit and synchronous sequential circuit differential asynchronous circuit:
Circuit Core logic useful combination circuit implementation;?????? Asynchronous sequential circuits are the most
The big drawback is the easy to produce burr;?????? Not conducive to device transplant;?????? Not conducive to static timing analysis (STA),
Verify design timing performance. Synchronous timing Circuit:?????? The core logic of the circuit is implemented by various triggers;
?????? The main signal and output signal of the circuit are generated at a certain clock along the driving trigger;??????
The synchronous sequential circuit can avoid the burr well;?????? facilitates device transplant;
Facilitates static time series analysis (STA) and verifies design timing performance.

23.led_value_r; LED value register (can be understood as an output register for LEDs)
24.assign {led3,led2,led1,led0} = ~led_value_r;
Note the characteristics and advantages of this assignment statement.
25. Note In the FPGA inside the counter time, that is, counter count to a certain, it is equivalent to the delay in the MCU function.
Require attention.
26. An example of a functional implementation of a combinatorial logic is shown below:
Always @ (num)//Note is the implementation of the combinatorial logic, where num changes, the corresponding Case statement executes.
Case (num)//num value displayed on two digital tubes
4 ' H0:SM_DBR <= seg0;

4 ' H1:SM_DBR <= seg1;
4 ' H2:SM_DBR <= seg2;
4 ' H3:SM_DBR <= seg3;
4 ' H4:SM_DBR <= seg4;
4 ' H5:SM_DBR <= seg5;
4 ' H6:SM_DBR <= seg6;
4 ' H7:SM_DBR <= Seg7;
4 ' H8:SM_DBR <= Seg8;
4 ' H9:SM_DBR <= seg9;
4 ' HA:SM_DBR <= Sega;
4 ' HB:SM_DBR <= SEGB;
4 ' HC:SM_DBR <= SEGC;
4 ' HD:SM_DBR <= segd;
4 ' HE:SM_DBR <= sege;
4 ' HF:SM_DBR <= SEGF;
Default:;
Endcase
27. Multipliers are the basic modules in many digital systems. In principle, it belongs to the category of combinatorial logic.
However, from the practical design of engineering, it often uses the method of sequential logic design, which belongs to the sequential logic
Category.
28. A basic requirement is the ability to apply the multiplier you have designed to the basic engineering application practice. The multiplier design has
Two methods, one is the combinatorial logic design, one is the sequential logic design.

29. Using timing logic to design a 16-bit multiplier, since it is designed using timing logic, it is necessary to use a clock signal to control
Multiplication operation.
30. Comparison of multipliers for combination and timing:
The design of time series can make the whole design have the characteristics of pipeline structure and can be applied in various engineering practice.
31. Be aware of the corresponding speed of the multiplier.
32. Several internal registers are set up here:
REG[15:0] Areg; Multiplier a Register
REG[15:0] Breg; Multiplier B Register
REG[31:0] Yout_r; Product Register
The reason this is set to register type is for the following
Complete the corresponding process of thought and accumulation.
33.max232 the TX and RX are kept high at the transfer level if the transmit data is not started.
34.SDRAM comparison SRAM
Because of the manufacturing process, SDRAM read and write slower than SRAM, and the capacity is larger than SRAM
But the control is relatively complex, and to keep refreshing.
SRAM is relatively simple to control and does not require a timed flush operation.
35. Whether to read or write a corresponding chip or to write a IIC communication protocol:
Then it must be clear that the timing diagram problem, that is, the reading and writing sequence must be clear.

36. The FPGA must be strong, there is no retreat.
37.hy57v641620et-7 is the most commonly used SDRAM capacity is 64M bit width is 16 bits.
38. Note that when the FPGA is downloading code, the as port is the code configured in the EPCs, the JTAG port is not configured in the EPCs
This requires attention.
39.M4K refers to the storage capacity of a 4K bit.
40. Note The design of the memory in the FPGA. How the Memory Works is:
Memory writes an address for each storage unit,
Therefore, only those storage units specified by the address can
Connect to the public IO and then perform a read/write operation to store the data.
Usually the memory is divided into:
Read-only memory (ROM), random memory (RAM) sequential memory and direct memory.
41. Read-only memory Rom:
ROM is an important sequential logic memory circuit, its logic function is in the choice of the address signal,
Reads the corresponding data from the specified storage unit. ROM can only read data, not modify or
Write the new data.

42. Note that for a corresponding application of the PLL, the clock generated by the PLL is stable from both frequency and phase, and
Its clock network delay is much smaller than the frequency divider clock generated by the internal logic.
43. Do the top-level ppl, if we want to see the corresponding output of C0 and C1, even in the simulation to see the corresponding results of its output
It is also required to define the C0 C1 as a reg (register) type, if not as an output, i.e. if it is an additional two always
Statement, then it is not necessary to define a variable of the register type, and the corresponding
function, you can (must) define a wire-type variable.
44. Be aware of the operation of the bus and bus in the FPGA.
45. Through some basic modules, such as adder and multiplier, some basic concepts of pipeline are discussed.
46. The so-called pipeline design is actually the larger, more hierarchical combination of logic circuit divided into several levels, in
Each level is inserted into the Register group and the intermediate data is staged. The K-class pipelining is the input from the combinational logic to the combinatorial logic
Output has exactly k register groups (divided into K-level, each level has a register group), the output of the first level
A circuit that is input at the next level and has no feedback.
47. The performance improvement of pipeline design is at the expense of more memory resources.
48. Pipeline processing is the most common means to improve the processing speed and throughput of combinatorial logic design.
49. Pipeline processing method can increase the clock frequency because the processing module is copied, it is the area in exchange for
A concrete embodiment of the idea of speed.
50. The categories of digital logic are ever-changing, but in essence, there are only two categories of combinatorial logic and sequential logic.
51. In general, combinatorial logic is used to complete simple logic functions such as multi-channel selectors, with, or, non-logical
Arithmetic operations such as arithmetic, addition, and multiplication. And the temporal logic can be used to produce a process related to the operation
(by Time beat) multiple control signal sequences.
52. Combinational logic, output is only the function of the current input logic level (with delay), independent of the original state of the circuit
Logic circuit. That is, there is no memory part of the logic circuit.
53. Timing logic, the output is not only the current input logic level function, but also the current state of the circuit is related
Logic circuit. Timing logic consists of multiple triggers and a network of multiple combined logical blocks. Synchronous timing Logic
Is the core of designing a complex digital logic system. The timing logic uses the status register to remember where it is currently
State.

54. Synchronous finite state machine is the basis of synchronous timing logic.
55. The output of the combined logic circuit is directly related to the level of each input signal. In a strict sense, its output
It is possible to change in every moment, and the output of synchronous timing logic is only when the clock jumps along the time
There may be changes.
56. Control of the data flow: The output must be saved in the Register group.
There are many register groups in the calculation circuit, which are intermediate data for staging operations. Between the Register groups
The precise control of data flow plays an extremely important role in the process of the algorithm implementation. This control is controlled by
Synchronous state machine implementation.
57. The multiplier is made up of doors, so there will be delays.
58. I will be able to learn the FPGA well ...
59. The complex synchronous state machine can be synthesized.
60. The departure input in the synchronous timing logic can be maintained at least one clock before a second trigger occurs.
It can be concluded that synchronous timing logic has a more reliable and simpler logic relationship than asynchronous sequential logic.
Using Verilog to design an integrated state machine must use synchronous timing logic.
61. Attention to the problem of competitive adventures in combinatorial logic ...
62. The use of asynchronous timing logic should be avoided in the actual design.
63. The rational allocation of computational structure and the improvement of operation efficiency are closely related to the design of the algorithm state machine.
64. Non-blocking assignment method: "=
It means that if there are a number of non-blocking assignments in the Begin end block
, their order of assignment is simultaneous and not assigned in order of precedence. As a matter of fact
They represent a value that simultaneously assigns the previous clock to the register at the same time.


All assigned values are stored in registers before 1:, and they have enough
To the data port of the assigned register.
In this way, the risk and competition generated by combinatorial logic can be avoided.
65. For randomly arrived data, you need to establish a synchronization mechanism, can be used to make the data through the RAM or FIFO
The method of caching and re-reading to achieve the purpose of data synchronization.
66. In communication systems, data is often organized by frame.
67. In order to avoid errors caused by asynchronous clock domains, it is common to use dual-RAM, dual-FIFO caching methods to complete asynchronous
Data transfer between the clock domains.
68. Write data in the input port using the pre-level clock, read the data at the output port using the current level clock, and have a buffer
Empty or Full control signal to manage the reading and writing of data to avoid data loss, can be very convenient and accurate
The completion of the asynchronous clock domain data exchange.
69. Synchronous state Machine-----A circuit that produces multiple enable control signals based on a synchronous clock.
70. Foreign asynchronous signals to be highly reliable in the introduction of chip circuits, must meet certain requirements, and must be
After careful synchronous processing, it is easy to create hidden circuit design.
71. Abstract a sequential logic into a synchronous finite state machine is a Verilog HDL module designed to be comprehensive in style
The key.
72.D triggers are used in the state machine design, please note.
73. In the design of high-speed circuits, it is often necessary to make the output of the state machine fully synchronized with the clock.
74. Use always and case statements to design finite state machines.
75. Most of the current complexes cannot be converted to a grid by using an asynchronous state machine described by Verilog HDL.
76. An event expression with the Posedge or Negedge keyword indicates the timing logic along the trigger, without Posedge
Or the Negedge keyword represents a combination logic or level-sensitive latch, or both.
77. Each time the timing always block can only be triggered by a clock hopping edge, the set or reset preferably also by the clock
Jump Edge trigger.
78. To assign a signal to the ' BX, the integrated device interprets it as an unrelated state, so that the integrated device generates the hardware
The simplest circuit.
79. The compilation of virtual modules is an important aspect of VERIOLG language application.
80. Note that the following statements are very important:
Always @ (Negedge Nconvst)
Fork
# T5 Nbusy=0; Note that this statement can be exchanged with the following @ statement
Position, this statement contains a lot of flavor, very heavy
Be well digested.
@ (Posedge nconvst)
Begin
#tconv Nbusy=1;
End
Join

81. Test the source code of the module, note that it can be written in different ways.
82.initial is often used for signal-giving when simulating.
83. In the always block, the assigned signal must be defined as the Reg type, which is characterized by the sequential logic circuit
determined by the.
84. Design of simple time series frequency divider logic circuit. and the use of conditional statements to achieve the counting frequency division sequence circuit.
Mastery: (1) Mastering the application of conditional statements in the design of simple sequential modules.
(2) Learn to apply counters in the Verilog module.
85. Learn the concepts and differences between blocking assignments and non-blocking assignments through experiments.
In sequential logic design, non-blocking assignment statements are often used, whereas in assign structures that implement combinatorial logic
, or a blocking assignment statement must be used in the always block structure.
86. In more complex combinational logic circuits, it is important to pay more attention to the advantages of using always blocks than assign.
87. Design complex timing logic with a high-level design approach, focusing on the abstraction of temporal logic as a finite state machine.
88. Master the basic method of the state machine design of access queue management. (FIFO)
89. Common timing logic circuits are counters, registers, latches, and memory.
90. Unlike registers with synchronous clock signal control, latches are controlled using a potential signal.
91. The shift register means that the binary data stored in the register can be controlled sequentially by the clock signal.
Move left or right, usually used in digital circuits for string and string conversions, numerical operations, etc.
92. The duty ratio is not a 1:1 even divider.
Module DIV6 (DIV6,CLK);
Output div6;
Input CLK;
Reg DIV6;
reg[2:0]cnt;
Always @ (Posedge CLK)
Begin
if (cnt==3 ' b101)
Begin Div6<=1;cnt<=0;end
Else
Begin Cnt<=cnt+1;div6<=0;end
93. Must be able to learn the FPGA.
94.FPGA if it is synchronous timing, it is not necessary to wait.
95. Is the Moduloe name of your Verilog code and your verilog between this file name itself is
There is no relationship between the file name and the module name can be the same, or can be different.
96. Connecting all CLK Together is a very interesting and
Great thing. End
Endmodule

Learning FPGA100 A noteworthy point (reproduced)