Linux Device Driver-communication with hardware (1)

I/O port and I/O memory

Each type of peripherals is controlled through read/write registers.

On the hardware layer, there is no conceptual difference between the memory and I/O Areas: they are accessed by sending level signals to the address bus and the control bus, then, read and write data through the data bus.

Because peripherals must match the I \ O bus, most of the popular I/O bus are based on the personal computer model and mainly x86 families: it provides independent lines and special CPU commands for reading and writing I/O Ports), so even if there is no separate I/O port address space for the processors, the read/write I \ O port must also be simulated when accessing peripherals. This feature is usually implemented by the North-South Bridge in the peripheral chipset PC) or additional circuits in the CPU ).

Linux implements I/O Ports on all computer platforms. But not all devices map registers

I/O port. Although ISA devices generally use I/O Ports, most PCI devices map registers to a memory address zone.

The memory method is usually the first choice. Because it does not need to use special processor commands, CPU

The core access memory is more efficient, and the compiler has more freedom to select the register allocation and addressing mode when accessing the memory.

I/O registers and general memory

When learning this part, you must first understand a concept: side

Effect, translated as marginal effect in the book, and translated as side effects in the second edition. I think no matter how it is translated, it is impossible to accurately express the meaning of the original author, so I personally think that remember side

Effect is good. The following describes the meaning of side effect. I will first post two existing online statements. Here, I would like to thank you for sharing these two ideas ):

The first statement:

3. side effect: the content of an address may change when it is read. For example, some device's interrupt status registers are automatically cleared once they are read. The operation of the I/O register has a side effect. Therefore, you cannot perform operations on it and cannot use the cpu cache.

Original Website:

Http://qinbh.blog.sohu.com/62733495.html

Second statement:

In my understanding, the I/O port is associated with the actual external device, and the access to the I/O port is used to control the external device. The "marginal effect" refers to the control device reading or writing) valid: access to the I/O port

The main purpose is the marginal effect. Unlike accessing normal memory, it only stores or reads a value in a single location, which has no other meaning. I understand it based on the arm platform.

The statement in the second edition of preface is "Side effects" rather than "marginal effects ".

Original Website:

Linux.chinaunix.net/bbs/viewthread.php? Tid = 890636 & page = 1 # pid6312646 "> http://linux.chinaunix.net/bbs/viewthread.php? Tid = 890636 & page = 1 # pid6312646

Based on the above two statements and my understanding of Linux driver 3rd, I personally think this can be explained as follows:

Side effect

It means that accessing the I/O register will not only affect the value of the storage unit as accessing the normal memory, more importantly, it may change the I/O port level of the CPU, the output sequence, or the CPU power on the I/O port.

To achieve CPU control. The significance of CPU in the circuit is to implement its side effect.

The main difference between I/O registers and RAM is that I/O register operations have side effect, while memory operations do not.

Because the access speed of the storage unit is crucial to the CPU performance, the compiler will optimize the source code, mainly by using the high-speed cache to save the value and rearranging the read/write command order. However, for I/O register operations, these optimizations may cause fatal errors. Therefore, the driver must ensure that high-speed cache is not used when operating the I/O registers, and the read/write instruction sequence cannot be re-arranged.

Solution:

Hardware cache: you only need to disable the hardware cache when the underlying hardware configuration (automatically or through Linux Initialization Code) is used to access the I/O Region (regardless of the memory or port.

Hardware Command Re-Sorting Problem: Set the memory barrier between the operations that the hardware (or other processors) must perform in a specific sequence ).