Linux interrupt mechanism, linux interrupt

Linux interrupt mechanism, linux interrupt

PC/AT microcomputer cascading 8259 Control System

The 8259 was introduced as part of Intel's MCS 85 family in 1976. the 8259A was encoded in the original PC introduced in 1981 and maintained by the PC/XT when introduced in 1983. A second 8259A was added with the introduction of the PC/. the 8259 has coexisted with the Intel APIC Architecture since its introduction in each Ric Multi-Processor PCs. modern PCs have begun to phase out the 8259A in favor of the Intel APIC Architecture. however, while not anymore a separate chip, the 8259A interface is still provided by the Southbridge chipset on modern x86 motherboards.

The main signal pins on an 8259 are as follows: eight interrupt input request lines named IRQ0 through IRQ7, an interrupt request output line named INTR, interrupt acknowledgment line named INTA, d0 through D7 for communicating the interrupt level or vector offset. other connections include CAS0 through CAS2 for cascading between 8259 s.

Up to eight slave 8259 s may be cascaded to a master 8259 to provide up to 64 IRQs. 8259 s are cascaded by connecting the INT line of one slave 8259 to the IRQ line of one master 8259.

There are three registers, an Interrupt Mask Register (IMR), an Interrupt Request Register (IRR), and an In-Service Register (ISR ). the IRR maintains a mask of the current interrupts that are pending acknowledgement, the ISR maintains a mask of the interrupts that are pending an EOI, and the IMR maintains a mask of interrupts that shoshould not be sent an acknowledgement.

End Of Interrupt (EOI) operations support specific EOI, non-specific EOI, and auto-EOI. A specific EOI specifies the IRQ level it is acknowledging in the ISR. A non-specific EOI resets the IRQ level in the ISR. auto-EOI resets the IRQ level in the ISR immediately after the interrupt is acknowledged.

Edge and level interrupt trigger modes are supported by the 8259A. Fixed priority and rotating priority modes are supported.

The 8259 may be configured to work with an 8080/8085 or an 8086/8088. on the 8086/8088, the interrupt controller will provide an interrupt number on the data bus when an interrupt occurs. the interrupt cycle of the 8080/8085 will issue three bytes on the data bus (corresponding to a CALL instruction in the 8080/8085 instruction set ).

The 8259A provides additional functionality compared to the 8259 (in particle buffered mode and level-triggered mode) and is upward compatible with it.

From http://en.wikipedia.org/wiki/Intel_8259>

There are two types of Interrupt signals: hardware interrupt and software interrupt. int 0x0 ~ Int 0x1F is a software interruption (exception) [fault + trap]. In Linux, 0x20 ~ 0x2F corresponds to the hardware request signal sent by the 8259A interrupt control chip IRQ 0x0 ~ IRQ 0xF, and set the program's system call interruption to int 0x80

In Linux, the kernel first uses a dummy interrupt vector (Interrupt Descriptor) to set default settings for all 256 descriptors in the Interrupt Descriptor Table, this dummy interrupt vector points to a default "No interrupt" processing process.

Hardware exception (int 0x0 ~ Int 0x01f) processing in the file traps. c

System Call interrupt int 0x80 is initialized in sched. c.

Interrupt mechanism in linux

Improve the running efficiency of the computer, accurate to the CPU efficiency. For example, if the program needs to format the disk, this operation takes 10 minutes. If there is no interruption mechanism, the CPU will always be there waiting for the Operation to complete, and then execute the subsequent tasks. Any request does not respond when waiting. If there is an interruption, the disk can be formatted first, and the CPU executes other tasks. When the formatting is complete, the CPU is interrupted and the formatting is completed.


What is the function of the linux driver to automatically detect the interrupt number ???

I use arm as an example. After the hardware sends an interrupt signal, the arm cpu jumps to the 0x18 address to execute the irq interrupt. This is the hardware mechanism. Is a hard rule.

We need to place a jump code at 0x18. After the jump code jumps to this jump code, we will perform some processing through the software and then jump to asm_do_irq to execute irq_desc-> irq_handler, in this handler, we will execute an irq_desc-> action-> handler. This hander hangs the interrupt handler in the irqaction list of the irq_desc structure through request_irq when writing the driver.

This is the linux interrupt mechanism. A sentence or two can be clearly stated.