Reprint Please specify the Source:Jiq ' s technical Blog
First, some confusing concepts are explained:
Interrupt Context: Span style= "font-family: Arial" > executing isr ( just pause cpu Go somewhere else in memory to execute a quick code " so cannot be toggled (
process context: Span style= "font-family: Arial" > non-disruptive context ( ( was switched )
Interrupt Stack: each processor has a dedicated interrupt stack. The previous interrupt handlers were the kernel stacks that used the interrupt process ( only one ), but the kernel stacks were getting more and more inadequate, so the interrupt handler had its own stack --- Interrupt stack, one per processor.
Interrupt Source:
(a) Peripheral request ( through a wire break,theCPU receives the signal from the INTR pin );
(b) Timer time ( programmable timer to complete the timing task );
(c) faulty hardware and procedures;
(d) software interruption ( software interrupt instructions are generated and are arranged by the program );
Interrupt Type:
(1) Hardware interrupt ( external interrupt ) : asynchronous interrupts generated by the hardware do not know when it will come.
(e) unshielded interrupts : The signal received from the INTR pin. It is usually sent over by the peripherals. Can be masked, if it is blocked, the interrupt controller registers a bit of the request in the register and waits until the interrupt is turned on to drive The INTR of the CPU. If there are multiple interrupt requests at the same time, the interrupt controller will first report a high-priority interrupt to the CPU before reporting a low-priority.
There are three ways to turn off an externally shielded interrupt:
---through CLI command will be in the flag register IF position is cleared, and all medium break is off.
Note Interrupt instruction is only closed in the disconnection, does not affect the software interruption and non-blocking interrupts;
---Block a particular interrupt line by interrupting the terminal screen register in the controller (IRQN) ;
---The device control register to control whether the device interrupts, shielding a single device;
Shielded Interrupt Response Time:
When the CPU receives a signal from the intr pin, it must have the following four conditions to respond:
(1) no bus request;
(2) Nothing but shielding interrupt request;
(3) The CPU is allowed to interrupt;
(4) The CPU executes the current instruction;
(f) Non-shielded interrupts : for example CPU power-down, etc.;
Non-shielded interrupt response time:
When the CPU receives a signal from the NMI pin, it must have the following two conditions to respond:
(1) no bus request;
(2) The CPU executes the current instruction;
(2) software interruption ( internal interrupt ) : by CPU internal command generated, is synchronous interrupt ( from the CPU Point of view ) .
(a) Fault: Error in instruction execution;
(b) Traps: by interrupting the descriptor book, for example INT3 , ETC., equivalent to immediately execute a jump instruction, jump to the ISR entry address ;
(c) Aborts: serious error;
Interrupt Vector Partitioning:
the interrupt vector is8a bit of that can have a total(0-255)Key, the processor uses0-31as internal interrupts, while the rest is free to use. General8259Aof theIRQ0Use +,IRQ1Use -..... Linuxused inInt 0x80as a system call.
Initialization of interrupts:
different hardware systems have different terminal controllers, so the kernel defines a irq_chip structure to describe the interrupt controller, the kernel does not need to be concerned with specific details. The device driver only needs to refer to its datasheet, provide the hardware related operation function, define a irq_chip object to be able.
Off Interrupt instruction CLI:
The software interrupt (int0x80) is not affected because the off interrupt is the corresponding bit of the interrupt request register, which disables the disconnection and only shuts down the external hardware interrupt, not the internal CPU software interrupt.
Linux kernel (ii) breaking basic concepts