Linux Memory Management---The difference between virtual address, logical address, linear address, physical address

The analysis of Linux memory management mechanism, can not leave the above several concepts, before introducing the above concepts, first from the "deep understanding of the Linux kernel," the book to extract a few paragraphs on the above noun explanation:

An explanation of the deep understanding of the Linux kernel

Logical addresses (Logical address)

Contains the address (a bit esoteric) used in machine language directives to specify an operand or an instruction. This type of addressing is particularly specific in 80x86 's well-known segmented structure, prompting Windows programmers to divide the program into several segments. Each logical address consists of a segment and an offset, which indicates the distance from the beginning of the segment to the actual address.

Linear address (linear address) (also known as virtual addresses)

is a 32-bit unsigned integer that can be used to represent addresses up to 4GB, and linear addresses are usually expressed in hexadecimal digits, ranging from 0x00000000 to 0xFFFFFFFF.

Physical addresses (physical address)

For memory chip-level memory unit addressing. They correspond to the electrical signals sent to the memory bus from the address pins of the microprocessor. A physical address is represented by a 32-bit or 36-bit unsigned integer. (In fact, this is the best understanding, is the real address)

PS: As you can see in the explanations below, logical addresses are sometimes treated as virtual addresses, but in "deep understanding of the Linux kernel" the linear addresses are considered virtual addresses.

First of all say: Linux about memory addressing can be divided into several stages, first by the segmentation mechanism, then have paging mechanism.

The paging mechanism is performed after the segment mechanism to complete the linear-physical address conversion process. The segment mechanism transforms the logical address into a linear address page mechanism to further convert the linear to a physical address.
Here is what I learned from the Internet to find information, but also add their own understanding
Ii. explanation of the second

Logical addresses (Logical address)

Refers to the part of the offset address that is generated by the program that is related to the segment. For example, you can read the pointer variable itself (& operation) in the C language pointer programming, which is actually the logical address, which is relative to the address of the data segment of your current process and is not coherent with the absolute physical address. Only in Intel Real mode will the logical address be equal to the physical address (because there is no fragmentation or paging mechanism for the real mode, the CPU does not perform automatic address translation), and the logic is the offset address of the code snippet in Intel protected mode (assuming that the code snippet, the data segment is exactly the same). The application programmer only has to deal with logical addresses, and the segmentation and paging mechanisms are completely transparent to you, and are only covered by system programmers. While the application programmer can manipulate the memory directly, it will only operate on the memory segments assigned to you by the operating system. (That is, the addresses we see in our application are logical addresses.) ）
If it is a programmer, then the logical address should be easy for you to understand. When we write C code, we often say that we define the offset of the first address of the struct, the entry offset of the function, the first address of the array, and so on. When we are focusing on these concepts, it is actually relative to your program. Not for the entire operating system. That is, the logical address is relative to the specific program you are compiling (or the process, which is actually executed as a process at run time). The entry address of your compiled program can be considered as the first address, and the logical address we can usually think of is in this program, the compiler assigns us the offset relative to this first address, or the first address as the starting point of a relative address value. (PS: In this sense, the logical address is an intra-paragraph offset, but that is a violation of the logical address definition, in the Intel segment is management, a logical address, is a segment identifier plus a specified segment within the offset of the relative address, expressed as [segment identifier: offset within paragraph])

When we double-click an executable program, it gives the operating system the entry address that the program runs on. The shell then passes the address of the executable file to the kernel. After entering the kernel, a new process is forked, and the new process allocates the corresponding memory area first. A well-known concept here is called copy on Write, which is a copy-on-write technique. This is not explained in detail, in short, after the new process has been fork out, the new process will get the entire PCB structure, and then call the EXEC function to go to the disk to load the code into the memory area. At this point, the PCB of the process is added to the queue of the executable process, and when the CPU is dispatched to this process, it is actually executed.

We can interpret the entry address of the program as the starting address of the logical address, that is, the start address of a program. And the related data of the program used later or the location of the code relative to the starting address (which is arranged by the compiler beforehand), constitutes what we call the logical address. A logical address is relative to a specific program (in fact a process, that is, the relative address of the program when it is actually run). There is a certain deviation in the details so long as you understand it.
In a word, the logical address is relative to the application. Historical background of logical address generation:

seeked, Intel's 8-bit machine 8080CPU, data bus (DB) is 8 bits, address bus (AB) is 16 bits. Then this 16-bit address information is also to be transmitted through the 8-bit data bus, but also in the data channel of the Scratchpad, as well as in the CPU registers and memory storage, but because AB is exactly the number of DB multiples, it will not create contradictions!

However, when the ascent to 16-bit machine, INTEL8086/8088CPU's design due to the current year IC integration technology and external packaging and PIN technology limitations, can not exceed 40 pins. But also felt that 8-bit machine original address addressing ability 2^16=64kb too little, but directly increased to 16 of the integer times even if ab=32 bit is not up to. So we can only temporarily increase the AB 4 to become 20 article. The

2^20=1MB has increased its addressing capacity by 16 times times. This, however, creates a contradiction between the 20-bit and DB 16-bit of AB, where the 20-bit address information cannot be transmitted on the DB or stored in 16-bit CPU registers and memory units. So the emergence of a CPU segment structure of the principle. Intel for compatibility, the ancient period of memory management has been preserved, there is a logical address

Linear addresses (Linear address)
Is the middle tier between the logical address and the physical address transformation. The program code generates a logical address, or an offset address in a segment, and a linear address is generated with the base address of the corresponding segment. If the paging mechanism is enabled, the linear address can then be transformed to produce a physical address. If the paging mechanism is not enabled, then the linear address is directly the physical address. Intel
80386 of the linear address space capacity is 4G (2 of the 32-time-32 address bus addressing).

We know that each computer has a CPU (we do it from a single CPU.) Multi-CPU should be the same, and eventually all the operation of instructions or data, and so on the operation of this CPU, and the CPU-related register is the storage memory device to hold some relevant information. Therefore, from the perspective of the CPU, we can easily divide the computer related devices or components into two categories: first, data or instructions to store memory devices (such as registers, memory, etc.), a data or instruction path (such as address lines, data lines, etc.). The essence of a linear address is "the address that the CPU sees". If we traced it, we would find that the linear address was the result of the development of Intel's X86 architecture. When the 32-bit CPU appears, it has an addressable range of 4GB, which is quite a huge number relative to the memory size, and we don't usually use that much memory. So this time the CPU can see the 4GB space and the actual capacity of the memory to create a gap. The linear address is used to describe the 4GB space that is visible to the CPU. We know that in a multi-process operating system, each process has a separate address space and has a separate resource. But for a particular moment, only one process runs on top of the CPU. At this point, the CPU sees the 4GB space occupied by this process, which is the linear address. What the CPU does is also for this linear space. It's called linear space, presumably because people think it's easier to understand how a continuous space is lined up. is actually the addressable range of the CPU.
For Linux, the CPU divides 4GB into two parts, 0-3GB for user space (also known as outer space), and 3-4GB as kernel space (also known as nuclear space). Operating system-related code, the kernel part of code data, is mapped to kernel space, and user processes are mapped to user space. As for how the system translates the linear address into the actual physical memory, the next article explains that there is no outside-section management and page management.

Physical addresses (physical address)
is the address signal addressing physical memory that appears on the external address bus of the CPU, which is the final result address of the address transformation. If the paging mechanism is enabled, the linear address is transformed into a physical address using the items in the page directory and the page table. If the paging mechanism is not enabled, then the linear address becomes the physical address directly.

Iii. Third Interpretation

Virtual Memory (Vsan)
Refers to the amount of memory that the computer presents that is much larger than the actual memory. So it allows programmers to compile and run programs that are much larger in memory than the actual system. This enables many large projects to be implemented on systems with limited memory resources. A very proper analogy is that you don't need a long track to get a train from Shanghai to Beijing. You only need long enough rails (say 3 km) to complete this task. The way to do this is to put the rear rails immediately in front of the train, as long as your operation is fast enough to meet the requirements, the train will be able to run like a complete track. This is the task that virtual memory management needs to accomplish. In Linux
0.11 cores, each program (process) is divided into a total capacity of 64MB of virtual memory space. So the program's logical address range is 0x0000000 to 0x4000000.

Sometimes we also refer to logical addresses as virtual addresses. Because similar to the concept of virtual memory space, the logical address is independent of the actual physical memory capacity. (This is a little bit different from the explanation above, and the next explanation goes as follows)
The "gap" between the logical address and the physical address is 0xc0000000, due to the exact difference between the virtual address, the linear address, and the physical address mapping. This value is specified by the operating system.

The conversion method of virtual address to physical address is architecture-related. Generally, there are two ways of segmenting and paging. Take the current x86 CPU as an example, the segmented paging is supported. The Memorymangement unit is responsible for converting from a logical address to a physical address. The logical address is the form of the segment identifier + offset within the segment, and the MMU can convert the logical address into a linear address by querying the segment table. If the CPU does not turn on paging, then the linear address is the physical address, and if the CPU turns on paging, the MMU also needs to query the page table to translate the linear address into a physical address:

Logical address----(segment table)---> Linear address-Physical address-(page table)
Different logical addresses can be mapped to the same linear address, and different linear addresses can be mapped to the same physical address; so it's a many-to-one relationship. In addition, the same linear address may be reloaded to another physical address after a page change occurs. So this many-to-one mapping also changes over time.

Iv. explanation of the fourth

1. Virtual address and logical address of the program (process)

The logical address (logicaladdress) refers to the offset address within the segment generated by the program. Applications only deal with logical addresses, and fragmented paging is transparent to the application. In other words, the & in C language, the symbolic address in assembly language, and the "M" of the embedded assembly in C are all logical addresses.

The logical address is Intel in order to be compatible, the ancient period of memory management to preserve the way. A logical address is a machine language instruction used to specify an operand or an address of an instruction. In the example above, we say that the 0x08111111 of the connector is the logical address of the assigned address. But I'm sorry to say that, it seems to be against the Intel Middle-management, the logical address requirements,"a logical address, is a segment identifier plus a specified paragraph within the offset of the relative address, expressed as [segment identifier: Intra-segment offset ], that is, The 0x08111111 in the example above should be represented as [A's code snippet identifier : 0x08111111], so that it's complete "
Linear address or virtual address : Similar to logical address, it is also an unreal address, if the logical address is the corresponding hardware platform segment management pre-conversion address, Then the linear address corresponds to the pre-conversion address of the hardware page memory.

1. Actual Physical memory address

The Physical Address (physicaladdress) is the addressing signal on the external address bus of the CPU, which is the final result of the address transformation, and a physical address always corresponds to a storage unit in real memory. For the 80386 protection mode, if the paging mechanism is turned on, the linear address is transformed from the page to the physical address. If the paging mechanism is not turned on, the linear address corresponds directly to the physical address. The page Catalog table entries and page table entries correspond to the physical addresses.

is the address signal addressing physical memory that appears on the external address bus of the CPU, which is the final result address of the address transformation. If the paging mechanism is enabled, the linear address is transformed into a physical address using the items in the page directory and the page table. If the paging mechanism is not enabled, then the linear address becomes the physical address directly.

The physical address is used for memory chip-level cell addressing, which corresponds to the address bus that the processor and CPU are connected to. This concept should be one of the best understanding of these concepts, but it is worth mentioning that although the physical address can be directly understood into the machine on the memory itself, the memory as a large array from 0 bytes to the maximum empty byte-by-bit number, and then the array is called the physical address, but in fact, This is just a hardware-to-software image, and the memory is not addressed in this way. So, it is "relative to address bus ", is more appropriate, but aside from the physical memory addressing mode of consideration, the physical address directly to the physical memory one by one corresponds, is also acceptable. Perhaps the wrong understanding is more favourable to the metaphysical image.

Linux0.11 the kernel data segment, the kernel code snippet base address is 0, so for the kernel, logical addresses are linear addresses. And because the 1-page Catalog table and 4 page tables fully map 16M of physical memory, the linear address is also the physical address. Therefore, for the linux0.11 kernel, logical address, linear address, physical address coincident.

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The        virtual address is the image description of the entire memory (not the one that is plugged into the machine). It is relative to the physical memory, it can be directly understood as"Unreal" ,"false " memory, for example, a 0x08000000 memory address, which does not 0x08000000-1 that address element in the large array on the physical address; Because modern operating systems provide a memory-managed image, virtual memory. The process uses the address in virtual memory, which is assisted by the operating system to "transform " it into a real physical address. This "Conversion " is the key to all the issues discussed. With such a pump, a program can use a much larger address space than the real physical address. (Rob Peter, pay Paul, banks do the same), and even multiple processes can use the same address. Not surprisingly, since the converted physical address is not the same. You can decompile the connected program and see that the connector has assigned an address to the program, for example, to invoke a function A, the code is not call a, it's called 0x0811111111, which means that the function The address of a has been fixed. There is no such thing as a "transform ", there is no concept of virtual address, and this does not work at all. Hold on, the question goes on again, and it won't hold up.
V. Summary

The

CPU converts an address in a virtual memory space into a physical address, which requires two steps: The first will be given a logical address (in fact, the offset within the paragraph, this must be understood!!!) ), the CPU uses its segment memory management unit to convert a logical address into a thread address, and then use its page-based memory management unit to convert to the final physical address.

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Linear address: Is the space or range that the CPU is capable of addressing.
Physical Address: Is the actual memory address in the machine. In other words, it is the range of memory capacity in the machine.
Logical address: is for the program. Generally expressed as seg:offset. (Programmers see the address themselves)
Therefore, to really compare the three, you should have the following relationship: The linear address is greater than or equal to the physical address (PS: But the address space is the same), and the logical address is greater than the linear address. The logical address is transformed into a linear address through the segment table, at which point the logical address is converted directly to the space the CPU can address if the paging mechanism is not turned on. If enabled, the transformation of the linear address to the physical address is done through the page table.
Therefore, the most accurate relationship of the three is: the logical address through the linear address to complete the mapping of physical address, the linear address in the three is completely the role of "bridge."

Either way, it's about the same, but the virtual address belongs to the three remaining questions.

This article describes the concept of four nouns, which are analyzed for four address conversions

The CPU translates the address in one virtual memory space into a physical address, which requires two steps (for example):

First, it will be given a logical address (in fact, the offset within the paragraph, this must be understood!!!) ), the CPU uses its segment memory management unit to convert a logical address into a thread address,

Second, use its page memory management unit to convert to the final physical address.

Doing this two conversions is really cumbersome and unnecessary because you can directly draw a linear address to the process. The reason for this redundancyis that Intel is completely compatible.

CPU-segment memory management, how logical addresses are converted to linear addresses

A logical address consists of two parts, the segment identifier : The offset within the segment. A segment identifier is made up of a 16-bit long field called a segment selector. The first 13 bits are an index number. The following 3 bits contain some hardware details,

The last two bits involve permission checks, which are not included here.

index number, or directly understand the array subscript-then it always corresponds to a set of the bar, it is what the index of what? This thing is "paragraph descriptor (segment descriptor)", hehe, the specific address of the segment descriptor describes a paragraph (for the "paragraph" of the word understanding, I think of it, took a knife, the virtual memory, cut into a number of sections--). In this way, a number of segment descriptors, a set of an array, called "segment Descriptor Table", so that you can go through the first 13 bits of the segment identifier, directly in the Segment descriptor list to find a specific segment descriptor, this descriptor describes a paragraph, I just the image of the paragraph is not very accurate, because look at what the descriptor inside That is how it is described, to understand what the paragraph is, each segment descriptor consists of 8 bytes, such as:

These things are very complex, although a data structure can be used to define it, but I only care about the same here, that is, the base field, which describes the starting position of a segment of the linear address.

Intel designed the idea that some global segment descriptors are placed in the Global Segment Descriptor List (GDT), and some parts, such as each process's own, are placed in the so-called "local segment Descriptor List (LDT)". When should the GDT be used, and when should the LDT be used? This is represented by the T1 field in the segment selector, = 0, which indicates the use of the LDT with Gdt,=1.

The address and size of the GDT in memory are stored in the GDTR control register of the CPU, while the LDT is in the LDTR register.

A lot of concepts, like tongue twisters. This picture looks more intuitive:

First, given a complete logical address [segment selector: offset address within paragraph],
1, see segment selector t1=0 or 1, know the current to convert is a GDT in the segment, or the LDT in the section, and then according to the corresponding register, get its address and size. We've got an array.
2, take out the segment selector in the first 13 bits, you can find the corresponding segment descriptor in this array, so that it is base, that is, the base address to know.
3, the base + offset, is to convert the linear address.

is quite simple, for the software, in principle, the need to convert the hardware required to prepare the information, you can let the hardware to complete the conversion. OK, let's see what Linux does.

Segment Management for Linux

Intel requires two conversions, which is compatible, but it is very redundant, oh, no way, hardware requirements to do so, software can only comply, how to have the same formalism.
On the other hand, some other hardware platforms do not have the concept of two conversions, and Linux also needs to provide a high-level image to provide a unified interface. So, the Linux segment management, in fact, just "tricked" the hardware.

According to Intel's original intent, the global use of GDT, each process of its own ldt--but Linux for all processes using the same field for instruction and data addressing. That is, user data segment, user code snippet, corresponding, kernel data segment and kernel code snippet. There is nothing strange about this, it is formality, as we write the year-end summary.

Include/asm-i386/segment.h

1. #define GDT_ENTRY_DEFAULT_USER_CS 14
2. #define __USER_CS (GDT_ENTRY_DEFAULT_USER_CS * 8 + 3)
4. #define GDT_ENTRY_DEFAULT_USER_DS 15
5. #define __USER_DS (GDT_ENTRY_DEFAULT_USER_DS * 8 + 3)
7. #define Gdt_entry_kernel_base 12
9. #define GDT_ENTRY_KERNEL_CS (gdt_entry_kernel_base + 0)
10. #define __KERNEL_CS (GDT_ENTRY_KERNEL_CS * 8)
12. #define GDT_ENTRY_KERNEL_DS (gdt_entry_kernel_base + 1)
13. #define __KERNEL_DS (GDT_ENTRY_KERNEL_DS * 8)

Copy Code

To replace the macro with a value:

1. #define __USER_CS 115 [00000000 1110 0 11]
2. #define __USER_DS 123 [00000000 1111 0 11]
3. #define __KERNEL_CS 96 [00000000 1100 0 00]
4. #define __KERNEL_DS 104 [00000000 1101 0 00]

Copy Code

The square brackets are the 16-bit two representations of the four segment selectors, and their index numbers and T1 field values can also be calculated.

1. __user_cs index= t1=0
2. __user_ds index= t1=0
3. __kernel_cs index= t1=0
4. __kernel_ds index= t1=0

Copy Code

The T1 are all 0, which means that the GDT is used, and then the corresponding 12-15 items (arch/i386/head) in the content of the initialized GDT are seen. S):

1. . Quad 0X00CF9A000000FFFF/* 0x60 kernel 4GB Code at 0X00000000 */
2. . Quad 0X00CF92000000FFFF/* 0x68 kernel 4GB data at 0x00000000 */
3. . Quad 0X00CFFA000000FFFF/* 0x73 user 4GB Code at 0x00000000 */
4. . Quad 0X00CFF2000000FFFF/* 0x7b user 4GB data at 0x00000000 */

Copy Code

As described in the preceding paragraph descriptor table, they can be expanded to find that the 16-31 bits are all 0, that is, the base site of the four segments is all 0.

Thus, given a paragraph offset address, according to the previous conversion formula, 0 + paragraph offset, converted to linear address, you can come to an important conclusion, "under Linux, the logical address and linear address always consistent (is consistent, not some people say the same), That is, the value of the offset field for the logical address is always the same as the value of the linear address. ”

Too many details, such as permission checks for a segment, are ignored. Oh.

In Linux, most processes do not use the LDT, unless you are using wine to simulate Windows programs.

Page-type memory management for CPUs

The page-type memory management unit of the CPU, which is responsible for translating a linear address into a physical address. From the management and efficiency point of view, the linear address is divided into fixed-length units, called pages (page), such as a 32-bit machine, the linear address can be a maximum of 4G, the 4KB is a page to divide, this page, the entire linear address is divided into a tatol_page[2^20] A large array of 2 of the 20 pages in a single page. This large array we call the page directory. Each directory entry in the directory is an address-the address of the corresponding page.

Another type of "page", which we call a physical page, or a page box, page frames. It is the paging unit that divides all physical memory into fixed-length management units whose length is typically one by one corresponding to the memory page.

Note here that this total_page array has 2^20 members, each member is an address (32-bit machine, one address is 4 bytes), then to represent such an array, it takes up 4MB of memory space. To save space, a two-level management-mode machine was introduced to organize paging units. The text description is too tired, look at the picture intuitively some:

Such as
1, paging Unit, the page directory is unique, its address in the CPU's CR3 register, is the starting point for address translation. The long march began to grow.
2, the process of each activity, because all have its own corresponding virtual memory (page directory is also unique), then it also corresponds to a separate page directory address. --run a process that needs to place its page directory address in the CR3 register and save it.
3, each 32-bit linear address is divided into three parts, page directory index (10-bit): Page table index (10-bit): offset (12-bit)
The conversion is performed according to the following steps:
1, remove the page directory address of the process from the CR3 (the operating system is responsible for the scheduling process, the address is loaded into the corresponding register);
2, according to the first ten linear address, in the array, find the corresponding index entry, because the introduction of the level two management mode, the page directory of the item, no longer the address of the page, but the address of a page table. (An array is introduced, and the address of the page is placed in the page table.)
3, according to the middle of the linear address 10 bits, in the page table (also array) to find the starting address of the page;
4, add the starting address of the page and the last 12 bits of the linear address, get the gourd we want eventually;

This conversion process should be said to be very simple. All by hardware, although a number of procedures, but save a lot of memory, or worthwhile. So, simply verify that:
1, such a level two mode is still able to represent the address of 4G;
Page Catalogs total: 2^10, which means there are so many page tables
Each eye table corresponds to: 2^10 page;
Addressable in each page: 2^12 bytes.
or 2^32 = 4GB

2, such a level two mode is really saving space;
By < in-depth understanding of computer systems > Interpretation, two-level mode space savings are achieved from two aspects:
A, if a page table entry in a page table is empty, then the two-page table that refers to it does not exist at all. This shows a huge potential savings, because for a typical program, most of the 4GB virtual address space will be unassigned;
B, only a single-level page table needs to always be in main memory. The virtual memory system can be created when needed, and the page will be paged into or out of the Level two page table, which reduces the stress of main memory. Only the most frequently used level two page table needs to be cached in main memory. --but Linux does not fully enjoy this benefit, and its page table directories and page tables associated with the assigned pages are memory-resident.

It is worth mentioning that, although the page directory and the page table items are 4 bytes, 32 bits, but they are only high 20 bits, low 12-bit shielding for 0--to the page table of the low 12 shield to 0, it is very well understood, because it is just a page size corresponding to each other, everyone into an integer increase. It's a lot easier to calculate. However, why should you also screen the page directory low 12 bit off it? Because by the same token, just block its low 10 bit on it, but I think, because 12>10, so that can make the page directory and page table use the same data structure, convenient.

This post only introduces the principle of general conversion, extended paging, page protection mechanism, PAE mode paging these troublesome things will not be wordy ... You can refer to other professional books.

5.Linux of page-memory management

In principle, Linux only needs to allocate the required data structure for each process, put in memory, and then in the scheduling process, the switch register CR3, the rest of the hardware to complete (hehe, in fact, much more complex, but I only analyze the most basic process).

It says I386 's two-level page management architecture, but some CPUs, there are three levels, or even four-tier architectures, and Linux provides a unified interface for each CPU in order to provide a higher level of image extraction. Provides a four-layer page management architecture that is compatible with these two-, three-, and four-level management architecture CPUs. These four levels are:

Page Global directory PGD (corresponding to the page directory just now)
Page Parent Directory PUD (newly introduced)
Page Intermediate Catalog PMD (also on newly introduced)
Page Table pt (corresponds to the page table just now).

The whole conversion is based on the principle of hardware conversion, just two more times the index of the array, such as:

So, for hardware that uses level two management architecture 32 bits, and now the four-level conversion, how can they work together in a coordinated way? Well, look at this situation, how to divide the linear address it!
From the hardware point of view, the 32-bit address is divided into three parts-that is, how to do not manage the software, the final implementation of hardware, but also only know the three boss.
From the software point of view, due to the introduction of more than two parts, that is, a total of five parts. --to make the hardware of the two-tier architecture aware of the five parts is also very easy, in the Address Division, the page ancestor directory and the page intermediate directory length is set to 0.
In this way, the operating system to see is five parts, hardware or its rigid three parts division, will not be wrong, that is to say, we build a harmonious computer system.

In this way, although superfluous, but considering the 64-bit address, using the four-tier conversion architecture of the CPU, we will no longer set the median two to 0, so that the software and hardware again harmony--The smoke is strong AH!!!

For example, a logical address has been converted to a linear address, 0x08147258, into two, which is:
0000100000 0101000111 001001011000
The kernel divides this address
PGD = 0000100000
PUD = 0
PMD = 0
PT = 0101000111
offset = 001001011000

Now to understand Linux for hardware tricks, because the hardware can not see so-called PUD,PMD, so, essentially requires PGD index, directly corresponds to the PT address. Instead of going to pud and PMD to look up arrays (although they are both in linear addresses, with lengths of 0,2^0 = 1, which means that they all have an array of array elements), how does the kernel properly arrange the addresses?
From the software's point of view, because it has only one, 32-bit entries, it can store exactly the same length of the address pointer as in the PGD. So the so-called first to the PUD, to the PMD to do mapping conversion, it becomes to maintain the original value unchanged, a change of hands on it. In this way, the implementation of "logically points to a pud, and then point to a PDM, but is physically directly pointed to the corresponding PT of this image, because the hardware is not known to have pud, PMD this thing."

Then to the hardware, hardware to this address division, see is:
Page directory = 0000100000
PT = 0101000111
offset = 001001011000
Well, first, according to 0000100000 (32), index in the page directory array, find the address of its element, take its high 20 bits, find the address of the page table, the address of the page table is dynamically allocated by the kernel, and then add an offset, is the final physical address.

Linux Memory Management---The difference between virtual address, logical address, linear address, physical address