Make command usage--go

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The code becomes an executable, called a compilation (compile), compiles this first, or compiles that (that is, the compiled arrangement), called Build.

Make is the most commonly used build tool, which was born in 1977 and is mainly used in C language projects. But in fact, any project that needs to be rebuilt as soon as a file changes, can be built with make.

This article describes the use of make commands and, from a simple perspective, does not require any basis, as long as the command line is used, it can be understood. My references are mainly Isaac Schlueter's makefile documentation tutorial and the GNU make manual.

(Pictured: Bozcaada Island, Turkey, July 2013)

First, the concept of make

Make the word, English means "making". The make command directly uses the meaning of making a file. For example, to make a file a.txt, you can execute the following command.

$ make A.txt

However, if you do enter this command, it will not work. Because the make command itself does not know how to do a.txt, someone needs to tell it how to invoke other commands to accomplish this goal.

For example, suppose the file a.txt relies on B.txt and c.txt, which is the product of the next two file connections (cat commands). So, make needs to know the following rules.

A.txt:b.txt c.txt    cat b.txt c.txt > A.txt

In other words, the make a.txt behind this command is actually divided into two steps: The first step is to confirm that B.txt and c.txt must already exist, and the second step uses the cat command to merge the two files and output them as new files.

Rules like this are written in a file called Makefile, and the Make command relies on this file for construction. The makefile file can also be written as makefile, or it may be specified as a different file name with a command line argument.

$ make-f rules.txt# or $ make--file=rules.txt

The above code specifies that the make command is built according to the rules in the Rules.txt file.

In summary, make is a tool that is built from a specified shell command. The rules are simple, you specify which file to build, what source files it depends on, and how to rebuild it when those files change.

Ii. format of the makefile file

The build rules are written in the makefile file, and to learn how to make commands, you must learn how to write makefile files.

2.1 Overview

The makefile file consists of a series of rules. The form of each rule is as follows.

<target>: <prerequisites> [tab]  <commands>

Above the first line of the colon before the section, called "Target", the part after the colon is called "preconditions" (prerequisites), the second line must be a tab key, followed by "command" (commands).

"Target" is required and cannot be omitted; "Preconditions" and "commands" are optional, but there must be at least one of them.

Each rule is clear about two things: what is the precondition for the build goal, and how to build it. Here is a detailed explanation of the three components of each rule.

2.2 Goal (target)

A target makes up a rule. The target is usually the file name, indicating the object to be constructed by the make command, such as the a.txt above. The target can be a file name, or multiple filenames, separated by a space.

In addition to the file name, the target can also be the name of an operation, which is called a pseudo-target (phony).

Clean:      rm *.o

The goal of the above code is clean, which is not a file name, but a name for the operation, belonging to the "pseudo-target", the function is to delete the object file.

$ make Clean  

However, if there is exactly one file in the current directory called clean, then this command will not execute. Because make discovers that the clean file already exists, it is considered unnecessary to rebuild and does not execute the specified RM command.

In order to avoid this situation, it is clear that clean is a "pseudo-target" and is written as follows.

. Phony:cleanclean:        RM *.o Temp

After declaring that clean is a pseudo-target, make does not check for a file called clean, but instead executes the corresponding command each time it runs. There are many built-in target names like. Phony, which can be viewed in the manual.

If the make command does not specify a target at run time, the first target of the makefile file is executed by default.

$ make

The above code executes the first target of the makefile file.

2.3 Pre-conditions (prerequisites)

A precondition is usually a set of filenames, separated by a space. It specifies the criteria for whether the "target" is rebuilt: as long as a pre-file does not exist or has been updated (the last-modification timestamp of the predecessor file is newer than the timestamp of the target), the "target" needs to be rebuilt.

Result.txt:source.txt    CP Source.txt Result.txt

In the above code, the precondition for building result.txt is source.txt. If Source.txt already exists in the current directory, make Result.txt can run normally, otherwise a rule must be written to generate the Source.txt.

Source.txt:    echo "This is the source" > Source.txt

In the above code, there is no precondition behind source.txt, which means it has nothing to do with any other files, so long as the file does not exist, it will be generated every time the make Source.txt is called.

$ make result.txt$ make Result.txt

The above command executes the make Result.txt two times in a row. The first execution creates a new source.txt and then creates a new result.txt. For the second execution, make discovers that Source.txt is not changed (the timestamp is later than Result.txt) and that no action is taken and Result.txt is not regenerated.

If you need to generate multiple files, you often use the following notation.

Source:file1 file2 File3

In the above code, source is a pseudo-target with only three predecessor files and no corresponding commands.

$ make Source

Once the make source command is executed, file1,file2,file3 three files are generated one time. This is much more convenient than the following wording.

$ make file1$ make file2$ make File3

2.4 Command (commands)

The command (commands) indicates how the target file is updated, consisting of one or more lines of shell commands. It is a specific instruction to build a "target", which usually results in the creation of a target file.

You must have a TAB key before each line of the command. If you want to use a different key, you can use built-in variables. Recipeprefix statement.

. Recipeprefix = >all:> echo Hello, world

The above code is used. RECIPEPREFIX specifies that the greater than sign (>) Overrides the TAB key. Therefore, the initial of each line of the command becomes the greater than sign, not the TAB key.

It is important to note that each line of command executes in a separate shell. There are no inheritance relationships between these shells.

Var-lost:    export Foo=bar    echo "foo=[$ $foo]"

After executing the above code (make Var-lost), the value of Foo is not taken. Because two lines of command are executed in two different processes. One solution is to write two lines of command in a single line, separated by semicolons.

Var-kept:    export foo=bar; echo "foo=[$ $foo]"

Another workaround is to add a backslash escape before the newline character.

Var-kept:    export foo=bar;     echo "foo=[$ $foo]"

The last method is to add. Oneshell: Command.

. Oneshell:var-kept:    export foo=bar;     echo "foo=[$ $foo]"

Iii. syntax of the makefile file 3.1 comments

The pound sign (#) represents a comment in the makefile.

# This is a comment result.txt:source.txt    # This is a comment    # This is also a comment 

3.2 Echo (echoing)

Normally, make prints each command and then executes it, which is called echo (echoing).

Test:    # This is testing

Execute the above rules and you will get the following result.

$ make Test# This is the test

You can turn off the echo by adding @ at the front of the command.

Test:    @# This is testing

Now execute make test and there will be no output.

Because during the build process, you need to know which command is currently executing, so you usually precede the comment and the plain display echo command with @.

Test:    @# This is the testing    @echo TODO

3.3 Wildcard characters

A wildcard character (wildcard) is used to specify a set of file names that match the criteria. The Makefile wildcard is consistent with Bash, with the main asterisk (*), question mark (? ) and [...]. For example, *.O represents all files with the suffix O.

Clean:        rm-f *.O

3.4 Pattern Matching

The make command allows matching of similar regular operations to file names, with the main match being%. For example, assume that the current directory has f1.c and f2.c two source files, you need to compile them into the corresponding object file.

%.O:%.c

Equivalent to the following notation.

F1.o:f1.cf2.o:f2.c

With the match%, you can build a large number of files of the same type with just one rule.

3.5 Variables and Assignment characters

Makefile allows you to use the equals sign to customize the variable.

txt = Hello worldtest:    @echo $ (TXT)

In the above code, the variable txt equals Hello world. When called, the variable needs to be placed in $ ().

Calling the shell variable requires a dollar sign before the dollar sign, because the make command escapes the dollar sign.

Test:    @echo $ $HOME

Sometimes, the value of a variable may point to another variable.

V1 = $ (v2)

In the above code, the value of the variable v1 is another variable v2. A question arises as to whether the value of V1 is extended (statically extended) at definition, or extended at run time (dynamically extended)? If the value of v2 is dynamic, the results of these two extensions may vary greatly.

To solve a similar problem, Makefile provides a total of four assignment operators (=,: =,?). =, + =), see StackOverflow for their differences.

VARIABLE = value# is extended at execution time, allowing recursive scaling. VARIABLE: = value# is extended when defined. VARIABLE? = value# Sets the value only if the variable is empty. VARIABLE + = value# Appends the value to the end of the variable. 

3.6 Built-in variables (implicit Variables)

The make command provides a set of built-in variables, such as $ (CC) to the currently used compiler, and $ (make) to point to the Make tool currently in use. This is primarily for cross-platform compatibility, and the detailed built-in variable list is shown in the manual.

Output:    $ (CC)-O output input.c

3.7 Automatic variable (Automatic Variables)

The Make command also provides some automatic variables whose values are related to the current rule. Mainly have the following several.

(1) [email protected]

[email protected] refers to the current target, which is the goal that the make command is currently building. For example, make Foo's [email protected] refers to Foo.

A.txt b.txt:     touch [email protected]

Equivalent to the following notation.

A.txt:    Touch a.txtb.txt:    Touch B.txt

(2) $<

$< refers to the first predecessor condition. For example, the rule is t:p1 P2, then $< refers to P1.

A.txt:b.txt C.txt    

Equivalent to the following notation.

A.txt:b.txt C.txt    

(3) $?

$? Refers to all preconditions that are newer than the target, separated by a space. For example, the rule is t:p1 P2, where P2 timestamp is newer than T, $? refers to P2.

(4) $^

$^ refers to all preconditions, separated by a space. For example, the rule is t:p1 P2, then $^ refers to P1 P2.

(5) $*

$* refers to the match% matching part, such as% matching f1.txt in the F1, $* represents F1.

(6) $ (@D) and $ (@F)

$ (@D) and $ (@F) refer to the directory name and file name of [email protected] respectively. For example, [email protected] is src/input.c, then the value of $ (@D) is SRC, and the value of $ (@F) is input.c.

(7) $ (<D) and $ (<f)

$ (<D) and $ (<f) point to $< 's directory name and file name, respectively.

For a list of all the automatic variables, see the manual. Here is an example of an automatic variable.

Dest/%.txt:src/%.txt    @[-d dest] | | mkdir dest    CP $< [email protected]

The above code copies the txt file under the SRC directory to the dest directory. First determine whether the Dest directory exists, if it does not exist, and then create a new, then,$< refers to the predecessor file (src/%.txt), [email protected] refers to the target file (dest/%.txt).

3.8 Judgment and circulation

Makefile uses Bash syntax to complete judgment and looping.

Ifeq ($ (CC), GCC)  libs=$ (LIBS_FOR_GCC) Else  libs=$ (normal_libs) endif

The above code determines whether the current compiler is GCC, and then specifies a different library file.

List = one threeall: For    i in $ (list), do         echo $ $i;     Done# equals all: For    I in one II three; do         echo $i;     Done

The result of running the above code.

Onetwothree

3.9 functions

Makefile can also use functions, in the following format.

$ (function arguments)# or ${function arguments}

Makefile provides a number of built-in functions that can be called. Here are a few common built-in functions.

(1) Shell function

Shell functions are used to execute shell commands

Srcfiles: = $ (shell echo Src/{00..99}.txt)

(2) Wildcard function

The wildcard function is used to replace the Bash wildcard in Makefile.

Srcfiles: = $ (wildcard src/*.txt)

(3) Replace function

The substitution function is written as: variable name + colon + substitution rule.

Min: $ (output:.js=.min.js)

The above code means to replace the. js in the variable output with the. Min.js.

Iv. Examples of Makefile

(1) Execute multiple targets

. Phony:cleanall cleanobj cleandiffcleanall:cleanobj Cleandiff        rm programcleanobj:        RM *.ocleandiff:        RM *.d Iff

The above code can call different targets, delete files with different suffix names, or call a target (cleanall) to delete all files of the specified type.

(2) Compiling C language Project

EDIT:MAIN.O kbd.o command.o display.o     cc-o edit main.o kbd.o command.o display.omain.o:main.c defs.h    cc-c ma IN.CKBD.O:KBD.C defs.h command.h    cc-c kbd.ccommand.o:command.c defs.h command.h cc-c    Command.cdisplay.o:di SPLAY.C defs.h    cc-c display.cclean:     rm edit MAIN.O kbd.o command.o display.o.phony:edit Clean

Today, the Make command is introduced here. In the next article I'll show you how to build a node. js project with make.

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Make command usage--go