Makefile comprehension (3)

How make works
1. Make target searches for makefile or makefile gnumakefile in the current directory or the file specified by-F (preferably makefile)

2. After finding the target, it will execute the corresponding goal (if there is no target, the first goal will be executed by default), and the final goal of the Target composition will be

3. If the target file does not exist or the modification time of the target dependent file is later than the modification time of the target file, execute this command to generate a new target

4. If the dependency exists and the dependency also serves as the target in makefile, the dependency file will be generated according to the above rules.

Makefile has five rules: Display rules, implicit rules, variables, files, and annotations.
Let's simply start
Note: If a string starting with # needs to be wrapped in a line, add \ at the end of the line to indicate that the next line is connected to a line.
Display rules: Use all commands to describe how to generate the target (the command must start with the tab key)
Implicit rules: Use the auto-derivation capability of make to generate some files on his own without generating commands or even targets for the target.
Variable: similar to the macro definition in C language.
File:

1. makefile
2. The include file is equivalent to opening the include file here.
3. Many pre-compiled command lines
It can be used repeatedly # define to customize some command lines to call when executing commands

#config.mkGCC = gccGXX = g++CFLAGS = -g -oCCFLAGS = -g -o

# Makefile # remarksinclude config. MK # file includeobjs: = Main. o fto. O start_fto.o gps_power.o # variable inc_file: = FTO. h gps_power.h # Source: = Main. c FTO. c start_fto.c gps_power.c #. phony: All # pseudo target all: gpsroutergpsrouter: $ (objs) # $ (GCC) $ (cflags) $ <# display rules $ (objs): $ (source) $ (inc_file) # use implicit rules
In makefile, you can also use the wildcard *. C to indicate all files ending with. c In the corresponding directory. If the corresponding file is used in makefile, but the file cannot be found, an error will be reported. When a command execution error occurs, an error will also be reported: Make cannot continue to execute, for example, if you need to create a new directory in makefile and the directory already exists, an error will be reported and make execution will be stopped. This error is tolerable, in this case, you can add the '-' character at the beginning of the command or '-' before the include command to avoid similar problems.
# Remarks-include config. MK # File Include if can't find the file skipobjs: = Main. o fto. O start_fto.o gps_power.o # variable inc_file: = FTO. h gps_power.h # Source: = Main. c FTO. c start_fto.c gps_power.c #. phony: All # pseudo target all: gpsroutergpsrouter: $ (objs) # $ (GCC) $ (cflags) $ <\-mkdir executable \ CP $ @ executable $ (objs): $ (source) $ (inc_file) # use implicit rules