Mbist: testable Design technology for Embedded Memory

The mbist technology can automatically implement RTL-level built-in self-testing circuits for memory units or arrays. The mbist EDA tool supports automatic implementation of multiple testing algorithms, you can automatically create BIST logic for one or more embedded memories and connect the BIST logic to the memory. In addition, the mbist structure can also include the automatic fault diagnosis function, this facilitates Fault Locating and the development of targeted test vectors. This article introduces the mbist Technology for Embedded Memory Design and discusses its circuit structure.

With the shrinking of the semiconductor process, the scale of IC design is getting bigger and bigger, and the highly complex IC products are facing increasingly severe challenges such as high reliability, high quality, low cost and shorter product marketing cycle. On the one hand, with the reduction of the semiconductor process size, embedded memory may have more and more types of defects. On the other hand, as the complexity of IC products increases, Rom, ram, and EEPROM are becoming more and more important in IC products.

The testable Design Technology of Embedded Memory includes:Direct Testing, testing with embedded CPU, and built-in self-testing technology (mbist).

Direct Testing Methods use automated testing devices for testing, which can easily implement a variety of high-quality testing algorithms. However, this method has some shortcomings,

1. The more complex the algorithm implemented on the ATE machine, the higher the requirement on the storage capacity of the ATE machine, the higher the test cost;
2. It is not easy to perform full-speed testing on embedded memory on the ATE machine. The higher the test clock frequency, the higher the test cost;
3. Due to the limitations of the peripheral pins of the chip, it is not realistic to directly test the large-capacity embedded memory in the chip.

The advantage of testing with embedded CPU is that you do not need to modify the design hardware, and the modification and Implementation of the test algorithm can be completed through flexible modification of the CPU software program. However, this method also has shortcomings,First, the CPU in the design is not directly connected to all the embedded memory. Second, writing or modifying software programs to implement testing algorithms requires a lot of manpower, in addition, it is difficult to test the memory of the CPU program.

The disadvantage of the mbist technology is that it increases the chip area and may affect the timing characteristics of the chip. However, as the memory capacity increases, the proportion of the chip area increased by this method is relatively small, in addition, this testing technology has many other technical advantages.

1. First, it can achieve the automation of testability design and automatically implement general memory testing algorithms to achieve high testing quality and low testing costs;
2. Secondly, the mbist circuit can use the system clock to perform a "full speed" test, so as to cover more defects generated and reduce the test time;
3. At last, it can provide self-diagnosis and self-repair functions for each storage unit. In addition, the initial test vector of mbist can be carried out on low-cost testing devices.

Therefore, from the perspective of high testing quality and low testing cost, mbist is the mainstream technology in the design of embedded memory testing.

Mbist Overview

BIST is a structured DFT technique that places the device's test structure inside the device. The BIST structure can be used to test various types of circuits, including random logical devices and regular circuit structures, such as data channels and memory. BIST circuits vary significantly depending on their application objects, but any type of BIST has a common purpose.The BIST structure can automatically generate various test vectors for the target circuit and compare the output response.The type of the target circuit is also diverse. It can be the overall chip design, or a structure in the design module or design module. In addition, the test Vector Generation and output comparison circuits may also be different.

Large and complex circuits usually contain multiple hard-to-test logic parts, even in the case of a large design with the best testability, it also requires a lot of test generation time, a lot of ate memory and ate test time, all of which are very expensive, but it is necessary to use the ATPG method for testing. In addition, because the memory defect type is different from the general logic defect type, the memory has a deep hierarchy in large-scale design. ATPG usually cannot provide a complete storage test solution, while the mbist technology can solve these problems.

BIST can provide a storage test solution without sacrificing the detection quality. In many cases, the BIST structure can completely eliminate or minimize the need for external test Vector Generation (as well as the storage capacity of the ATE machine) and test application time.The designer can execute the mbist circuit within a design and easily perform full-speed testing because the mbist circuit is adjacent to the tested memory. The designer can also run the mbist process from a higher level of design..

The mbist circuit is designed for Ram and Rom models. As mentioned above, because the memory defect type is different from the general logic defect type, the detection of Ram and Rom is different from the detection of random logic, mbist uses effective circuits and algorithms to detect Common Defects in Ram and Rom. The mbist circuit can also generate multiple test vectors based on various algorithms, each of which focuses on testing a specific circuit type or error type. Compared circuits have a variety of unique implementations, including comparator and tag analyzer.

The memory circuit model consists of three basic modules: Address decoder, read/write control logic, and storage unit array.

Mbist Architecture

Mbist is typically designed to test one or more types of memory defects using one or more algorithms. The mbist circuit includes testingVector Generation circuit, bist control circuit, Response AnalyzerThree parts.

The test vector generation circuit can generate multiple test vectors. The test vector content produced by the circuits implemented by different test algorithms is also different. The BIST control circuit is usually implemented by the state machine, the BIST controls the read/write operations on the memory. The response analyzer can be implemented either by a comparator or by using the multi-input shift register (Misr) circuit of the compressors. It can respond to known normal memories, compare the actual memory model response and Detect Device errors.

As shown in the mbist circuit 3 Implemented by the comparator, the circuit provides two signals, tst_done and fail_h, to notify the System of the status and results of the testing process. Tst_done is set to valid at the end of the test. If any errors are found during the test, the fail_h signal is set to valid until the test ends. The mbist circuit 4, which is implemented by the compression tool, provides the Misr-based comparison technology. After the test is completed, the compressed label register result can be output.

In general, the mbist circuit can not only filter out the failed devices, but also automatically analyze the cause of the failure. At this time, the test data is also used to analyze the specific address space for locating the memory failure.

In addition, the special mbist circuit provides self-diagnosis and self-repair functions. The built-in self-analysis module is introduced into the mbist circuit. The BIST module outputs the corresponding control signal r2r1r0 Based on invalid data and address information, the system directs the read/write operations on the memory Invalid Address Space to the Redundancy Design for self-repairing.

The mbist circuit usually also includes the BIST collar module. The BIST collar module includes the streamline processing circuit, scanning bypass circuit, multiplexing circuit, and Misr circuit, the scanning bypass circuit is most commonly used (figure 5 ).

Mbist implementation and EDA tools

The mbist tool allows designers to spend more time designing work, rather than worrying about testing issues. The tool has built-in knowledge necessary to develop a memory to test and manage BIST circuits. The fault diagnosis circuit generated by the tool allows designers to identify and analyze fault data. It can generate corresponding testscripts to facilitate the verification of the peripheral circuit logic of mbist. It can also generate corresponding automatic script files to facilitate the integrated logic automation operation. In addition, for any EDA tool, to work effectively, it must be able to adapt to the existing design process of the designer and follow various industry standards.

Mbistarchitect is a mbist automated EDA tool provided by mentor. It can develop embedded test circuits for one or more embedded memory, and automatically implement RTL-level built-in self-test circuits for memory units or arrays. It supports multiple test algorithms to automatically create BIST logic for one or more embedded memories, connect the BIST logic to the memory, and share the BIST controller between multiple memories, implement Parallel testing to shorten the testing time and save the chip area. The mbist structure can also include the automatic fault diagnosis function, facilitating Fault Locating and developing targeted test vectors.

Mbist: testable Design technology for Embedded Memory