One of timequest Learning

 

Edn blog highlightsArticleAuthor:Codeman

Set_input_delay/set_output_delay

Define data arrival time on the input port related to the clock defined by the clock option. You can define the input delay to be related to the rising or falling edge.

If the input delay is related to a simple generation clock, the clock arrival time of the generation clock must be added to the data arrival time.

The input latency can be defined to be related to the port in the clock network. The clock arrival time of the reference port must be added to the data arrival time.

The input latency can contain the clock source latency. By default, the related clock source latency is added to the input latency. However, when the-source_latency_0000ded option is defined, the clock source latency is not added, because it is not used as the timing factor of input delay value.

Max is used for clock establishment time or recovery verification, and Min is used for clock persistence clock or removal (removal) verification.

The above content is taken from Quartus help, which basically defines what many senior colleagues have already said on edn.

Let's take a look at the following simple example. The two-level trigger comes from

Http://www.altera.com.cn/support/examples/timequest/exm-timequest.html

In a simple example, only when the clock cycle constraint is added,

 

 
  Create_clock-Period10.000 -Name clk_in [get_ports {clk_in}]
 

 

 

Only one path analysis is obtained by using timequest analysis, reg1 to reg2. The sequence diagram is as follows:

Clock arrival time = latch edge + clock network delay to destination register

11.110 = 10 plus 1.110

Data required time = clock arrival time-U/Tsu

11.125 = 11.110-(-0.015)

Data arrival time = launch edge + clock network delay source register + U/TCO + register-to-register Delay

1.438 = 0 + 1.148 + 0.199 + 0.091

Clock setup slack = data required time-data arrival time

9.687 = 11.125-1.438

 

  Set_input_delay-Clock {clk_in}-Add_delay1.200[Get_ports {data_in}]

Set_output_delay-Clock {clk_in}-Add_delay2.000[Get_ports data_out]

 

Run timequest again. You can see three paths for analysis.

1) data_in to reg1

 

2) reg1 to reg2

 

3) reg2 to data_out

We can see that input delay is added to the input path in data arrival time, and output delay is subtracted from data required time in the output path, which affects setup and hold time respectively.