Online debugging of Quartus II

We didn't pay much attention to it before. Altera provided many online debugging methods in Quartus,

In section V. In-system design debugging of Quartus II version 7.2 handbook Volume 3: verification, five methods are introduced in Chapter 5: 1. Quick Design Debugging Using Signalprobe Signal Probe The method does not affect the original design functions and layout wiring, but connects the signals to be observed and debugged to the reserved or unused I/O interfaces by adding additional wiring. The signal level will have a certain delay along with the wiring. It is not suitable for observation and debugging of High-speed and large-capacity signals, or board-level timing analysis. Its advantage is that it does not affect the original design, and the additional resource consumption is almost zero. In debugging, it does not need to be connected to other cables such as JTAG, which can minimize the compilation or re-Compilation Time. 2. Design Debugging Using SignalTap II embedded Logic Analyzer Online Logic Analyzer To a large extent, it can replace the expensive logic analyzer to save costs for development. At the same time, it also saves the original tedious connection work for the debugger, some board-level external devices can easily capture the observed signals. If the regional constraints on the design module can also minimize the impact of the use of online logic analyzer on the design. The sampling storage depth and width of the online logic analyzer are subject to the resource size of FPGA Devices to a certain extent. To use this method, you must use the JTAG interface. The sampling frequency can reach 200 MHz (if supported by the device) or higher, without worrying about signal integrity issues like external debugging devices. 3. Logic Analyzer Interface Using External logic analyzers Logical analyzer Interface For external logic analyzer. The debugger can set multiple signals in the FPGA device to map to an I/O interface that is pre-reserved or temporarily unavailable, this allows you to observe multiple groups of signals in FPGA through a small number of I/O interfaces. 4. In-system updating of memory and constants using In-system memory Content Editor Online storage content editing Debugging of embedded memory content or constants in the design. In this way, you can overwrite or read the embedded storage content or constants in the project online. For some applications, you can verify the design by modifying the storage content online and observe the response. You can also read the current storage content online under different incentives to verify the design. 5. Design Debugging Using In-System sources and probes This method is to link a custom register to an FPGA device through examples. These register chains communicate with Quartus II through the JTAG interface, which can drive some input node signals inside the FPGA device and sample some output node signals. This allows the debugger to add incentives to the FPGA and observe the response without using external devices. Here, we can easily observe the changes of the registers in FPGA, or even observe the changes in real time. Basically, it is different from an external oscilloscope or logic analyzer. It is quite convenient to use. It is just a simple case-based connection ing that can be used after re-compilation. In addition to these five types, there is another powerful tool, that is
6. Virtual JTAG